FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 3

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
Intel
®
82801DBM ICH4-M Datasheet
®
82801DBM ICH4 Features
The Intel
from published specifications. Current characterized errata are available on request.
PCI Bus Interface
Integrated LAN Controller
Integrated IDE Controller
USB
AC'97 Link for Audio and Telephony CODECs
Interrupt Controller
New: 1.5 V operation with 3.3 V I/O
Timers Based on 82C54
— Supports PCI Revision 2.2 Specification at
— 133 MB/sec maximum throughput
— Supports up to 6 master devices on PCI
— One PCI REQ/GNT pair can be given higher
— Support for 44-bit addressing on PCI using DAC
— WfM 2.0 and IEEE 802.3 compliant
— LAN Connect Interface (LCI)
— 10/100 Mbit/sec ethernet support
— Supports “Native Mode” register and interrupts
— Independent timing of up to 4 drives, with separate
— Ultra ATA/100/66/33, BMIDE and PIO modes
— Tri-state modes to enable swap bay
— Includes 3 UHCI host controllers that support 6
— New: Includes 1 EHCI high-speed USB 2.0 Host
— New: Supports a USB 2.0 high-speed debug port
— Supports wake-up from sleeping states S1-M–S5
— Supports legacy keyboard/mouse software
— New: Third AC_SDATA_IN line for three codec
— Supports AC ’97 2.3
— New: Independent bus master logic for 7 channels
— Separate independent PCI functions for audio and
— Support for up to six channels of PCM audio
— Supports wake-up events
— Support up to 8 PCI interrupt pins
— Supports PCI 2.2 message signaled interrupts
— Two cascaded 82C59 with 15 interrupts
— Integrated I/O APIC capability with 24 interrupts
— Supports serial interrupt protocol
— Supports processor system bus interrupt delivery
— 5V tolerant buffers on IDE, PCI, USB over-current
— System timer, refresh request, speaker tone output
®
33 MHz
arbitration priority (intended for external 1394
host controller)
protocol
primary and secondary IDE cable connections
external ports
Controller that supports all six ports
support
(PCM In/Out, Mic 1 input, Mic 2 input, modem
in/out, S/PDIF out)
modem
output (full AC3 decode)
and legacy signals
82801DBM ICH4-M may contain design defects or errors known as errata which may cause the products to deviate
Power Management Logic
External Glue Integration
Enhanced Hub Interface buffers improve routing
flexibility (Not available with all Memory Controller
Hubs)
Firmware Hub (FWH) Interface supports BIOS
memory size up to 8 MB
Low Pin Count (LPC) Interface
Enhanced DMA Controller
Real-Time Clock
System TCO Reduction Circuits
SMBus
GPIO
Package 31x31 mm 421 BGA
— ACPI 2.0 compliant
— ACPI-defined power states (C1–C4, S1-M,
— ACPI power management timer
— Support for “Intel
— (Support for “Deeper Sleep” power state
— PCI CLKRUN# and PME# support
— SMI# generation
— All registers readable/restorable for proper resume
— Integrated pull-up, pull-down and series
— Integrated Pull-down and Series resistors on USB
— Supports two Master/DMA devices.
— Two cascaded 8237 DMA controllers
— PCI DMA: Supports PC/PCI — Includes two
— Supports LPC DMA
— Supports DMA collection buffer to provide
— 256-byte battery-backed CMOS RAM
— Timers to generate SMI# and Reset upon detection
— Timers to detect improper processor reset
— Supports ability to disable external devices
— New: Hardware packet error checking
— New: Supports SMBus 2.0 Specification
— Host interface allows processor to communicate
— Slave interface allows an external microcontroller
— Compatible with most 2-wire components that are
— TTL, open-drain, inversion
S3–S5)
processor power control
from 0 V suspend states
termination resistors on IDE, processor interface
PC/PCI REQ#/GNT# pairs
Type-F DMA performance for all DMA channels
of system hang
via SMBus
to access system resources
also I
2
C compatible
®
SpeedStep
TM
technology”
3