FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 167

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.13
5.13.1
5.13.1.1
5.13.1.2
Intel
®
82801DBM ICH4-M Datasheet
Note: Voltage ID from the processor can be read via GPI signals.
System Management (D31:F0)
The ICH4 provides various functions to make a system easier to manage and to lower the Total
Cost of Ownership (TCO) of the system. Features and functions can be augmented via external
A/D converters and GPIO, as well as an external microcontroller.
The following features and functions are supported by the ICH4:
Theory of Operation
The System Management functions are designed to allow the system to diagnose failing
subsystems. The intent of this logic is that some of the system management functionality be
provided without the aid of an external microcontroller.
Detecting a System Lockup
When the processor is reset, it is expected to fetch its first instruction. If the processor fails to fetch
the first instruction after reset, the TCO timer times out twice and the ICH4 asserts PCIRST#.
Handling an Intruder
The ICH4 has an input signal, INTRUDER#, that can be attached to a switch that is activated by
the system’s case being open. This input has a two RTC clock debounce. If INTRUDER# goes
active (after the debouncer), this will set the INTRD_DET bit in the TCO_STS register. The
INTRD_SEL bits in the TCO_CNT register can enable the ICH4 to cause an SMI# or interrupt.
The BIOS or interrupt handler can then cause a transition to the S5 state by writing to the SLP_EN
bit.
The software can also directly read the status of the INTRUDER# signal (high or low) by clearing
and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder
function is not required.
•
•
•
•
•
Processor present detection
Various Error detection (e.g., ECC Errors) Indicated by Host Controller
Intruder Detect input
Detection of bad FWH programming
Ability to hide a PCI device
— Detects if processor fails to fetch the first instruction after reset
— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt
— Can generate TCO interrupt or SMI# when the system cover is remove
— INTRUDER# allowed to go active in any power state, including G3
— Detects if data on first read is FFh (indicates unprogrammed FWH)
— Allows software to hide a PCI device in terms of configuration space through the use of a
device hide register (See
Section
8.1.26)
Functional Description
167