FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 138

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.11.1.4
5.11.1.5
5.11.1.6
5.11.1.7
138
Table 5-31. NMI Sources
NMI
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in
STPCLK# and CPUSLP# Signals
The ICH4 power management logic controls these active-low signals. Refer to
more information on the functionality of these signals.
CPUPWRGOOD Signal
This signal is connected to the processor’s PWRGOOD input. To allow for Intel SpeedStep
technology support, this signal is kept high during an Intel SpeedStep technology state transition to
prevent loss of processor context. This is an open-drain output signal (external pull-up resistor
required) that represents a logical AND of the ICH4’s PWROK and VGATE / VRMPWRGD
signals.
DPSLP#
This active-low signal controls the internal gating of the processor’s core clock. This signal
behaves identically to the STP_CPU# signal to effectively stop the processor’s clock (internally) in
the states in which STP_CPU# can be used to stop the processor’s clock externally.
SERR# goes active (either internally, externally
via SERR# signal, or via message from the MCH)
IOCHK# goes active via SERIRQ# stream
(ISA system Error)
Cause of NMI
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).
Intel
®
Comment
82801DBM ICH4-M Datasheet
Section 5.12
Table
for
5-31.