FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 252

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.19.2.23
252
Table 5-102. Output Tag Slot 0
Register Access
In the ICH4 implementation of the AC-link, up to three codecs can be connected to the
AC_SDOUT pin. The following mechanism is used to address the primary, secondary, and tertiary
codecs individually.
The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits [18:12] of
slot 1 are used for the register index. For I/O writes to the primary codec, the valid bits [14:13] for
slots 1 and 2 must be set in slot 0, as shown in
address, and slot 2 is used to transmit data. For I/O reads to the primary codec, only slot 1 should
be valid since only an address is transmitted. For I/O reads only slot 1 valid bit is set, while for I/O
writes both slots 1 and 2 valid bits are set.
The secondary and tertiary codec registers are accessed using slots 1 and 2 as described above,
however the slot valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec ID bits [1:0]
(bit 0 and bit 1 of slot 0) is set to a non zero value. This allows the secondary or tertiary codec to
monitor the slot valid bits of slots 1and 2, and bits [1:0] of slot 0 to determine if the access is
directed to the secondary or tertiary codec. If the register access is targeted to the secondary or
tertiary codec, slot 1 and 2 will contain the address and data for the register access. Since slots 1
and 2 are marked invalid, the primary codec will ignore these accesses.
When accessing the codec registers, only one I/O cycle can be pending across the AC-link at any
time. The ICH4 implements write posting on I/O writes across the AC-link (i.e., writes across the
link are indicated as complete before they are actually sent across the link). In order to prevent a
second I/O write from occurring before the first one is complete, software must monitor the CAS
bit in the Codec Access Semaphore register which indicates that a codec access is pending. Once
the CAS bit is cleared, then another codec access (read or write) can go through. The exception to
this being reads to offset 54h/D4h/154h (slot 12) which are returned immediately with the most
recently received slot 12 data. Writes to offset 54h, D4h, and 154h (primary, secondary and tertiary
codecs), get transmitted across the AC-link in slots 1 and 2 as a normal register access. Slot 12 is
also updated immediately to reflect the data being written.
The controller will not issue back to back reads. It must get a response to the first read before
issuing a second. In addition, codec reads and writes are only executed once across the link, and are
not repeated.
12:3
1:0
Bit
15
14
13
2
Primary Access
Example
00
X
1
1
1
0
Secondary Access
Example
01
X
1
0
0
0
Table
Frame Valid
Slot 1 Valid, Command Address bit (Primary codec only)
Slot 2 Valid, Command Data bit (Primary codec only)
Slot 3–12 Valid
Reserved
Codec ID (00 reserved for primary; 01 indicate secondary;
10 indicate tertiary)
5-102. Slot 1 is used to transmit the register
Intel
®
Description
82801DBM ICH4-M Datasheet