FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 366

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.8.1.6
366
TRP_FWD_EN—IO Monitor Trap Forwarding Enable Register
(PM—D31:F0)
Offset Address:
Default Value:
Lockable:
Power Well:
The ICH4 uses this register to enable the monitors to forward cycles to LPC, independent of the
POS_DEC_EN bit and the bits that enable the monitor to generate an SMI#. The only criteria is
that the address passes the decoding logic as determined by the MON[n]_TRP_RNG and
MON_TRP_MSK register settings.
Bit
3:0
7
6
5
4
MON7_FWD_EN — R/W.
0 = Disable. Cycles trapped by I/O Monitor 7 will not be forwarded to LPC.
1 = Enable. Cycles trapped by I/O Monitor 7 will be forwarded to LPC.
MON6_FWD_EN — R/W.
0 = Disable. Cycles trapped by I/O Monitor 6 will not be forwarded to LPC.
1 = Enable. Cycles trapped by I/O Monitor 6 will be forwarded to LPC.
MON5_FWD_EN — R/W.
0 = Disable. Cycles trapped by I/O Monitor 5 will not be forwarded to LPC.
1 = Enable. Cycles trapped by I/O Monitor 5 will be forwarded to LPC.
MON4_FWD_EN — R/W.
0 = Disable. Cycles trapped by I/O Monitor 4 will not be forwarded to LPC.
1 = Enable. Cycles trapped by I/O Monitor 4 will be forwarded to LPC.
Reserved
No
Core
C0h
00h
Description
Attribute:
Size:
Usage:
Intel
®
82801DBM ICH4-M Datasheet
R/W (Special)
8 bits
Legacy Only