FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 274

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LAN Controller Registers (B1:D8:F0)
7.1.22
7.1.23
274
PM_CAP — Power Management Capabilities
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
PMCSR — Power Management Control/Status Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
14:13
15:11
12:9
Bit
8:6
2:0
Bit
7:5
3:2
10
15
9
5
4
3
8
4
PME Support — RO. Hardwired to 11111b. This 5-bit field indicates the power states in which the
LAN Controller may assert PME#. The LAN* Controller supports wake-up in all power states.
D2 Support — RO. Hardwired to 1 to indicate that the LAN Controller supports the D2 power state.
D1 Support — RO. Hardwired to 1 to indicate that the LAN Controller supports the D1 power state.
Auxiliary Current — RO. Hardwired to 000b to indicate that the LAN Controller implements the Data
registers. The auxiliary power consumption is the same as the current consumption reported in the
D3 state in the Data register.
Device Specific Initialization (DSI) — RO. Hardwired to 1 to indicate that special initialization of this
function is required (beyond the standard PCI configuration header) before the generic class device
driver is able to use it. DSI is required for the LAN Controller after D3-to-D0 reset.
Reserved
PME Clock — RO. Hardwired to 0 to indicate that the LAN Controller does not require a clock to
generate a power management event.
Version — RO. Hardwired to 010b to indicate that the LAN Controller complies with of the PCI
Power Management Specification, Revision 1.1 .
PME Status — R/WC.
0 = Software clears this bit by writing a 1 to the bit location. This also deasserts the PME# signal
1 = Set upon occurrence of a wake-up event, independent of the state of the PME Enable bit.
Data Scale — RO. This field indicates the data register scaling factor. It equals 10b for registers
zero through eight and 00b for registers nine through fifteen, as selected by the “Data Select” field.
Data Select — R/W. This field is used to select which data is reported through the Data register and
Data Scale field.
PME Enable — R/W. This bit enables the ICH4’s integrated LAN controller to assert PME#.
0 = The device will not assert PME#.
1 = Enable PME# assertion when PME Status is set.
Reserved
Dynamic Data — RO. Hardwired to 0 to indicate that the device does not support the ability to
monitor the power consumption dynamically.
Reserved
and clears the PME status bit in the Power Management Driver Register. When the PME#
signal is enabled, the PME# signal reflects the state of the PME status bit.
DE
0000h
E0
7E21h
–
–
E1h
DFh
Description
Description
Attribute:
Size:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
RO
16 bits
R/WC, R/W, RO
16 bits