FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 319

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.1.24
Intel
®
82801DBM ICH4-M Datasheet
BACK_CNTL—Backed Up Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
3:0
Bit
7
6
5
4
0 = The reset state of the secondary IDE pins will be driven/tri-state (depending upon the pin).
1 = The reset state of all secondary IDE pins will be tri-state. (Default)
Primary Reset State (PRS) — R/W.
0 = The reset state of the primary IDE pins will be driven/tri-state (depending upon the pin).
1 = The reset state of all primary IDE pins will be tri-state (Default).
Top-Block Swap Mode (TOP_SWAP) — R/W.
0 = ICH4 will not invert A16. This bit is cleared by RTCRST# assertion, but not by any other type of
1 = ICH4 inverts A16 for cycles targeting FWH BIOS space (Does not affect accesses to FWH
CPU BIST Enable (CPU_BIST_EN) — R/W.
0 = Disable.
1 = The INIT# signal will be driven active when CPURST# is active. INIT# will go inactive with the
NOTE: This bit is in the Resume well and is reset by RSMRST#, but not by PCIRST# nor CF9h
CPU Frequency Strap (FREQ_STRAP[3:0]) — R/W. These bits determine the internal frequency
multiplier of the processor. These bits can be reset to 1111 based on an external pin strap or via the
RTCRST# input signal. Software must program this field based on the processor’s specified
frequency. Note that this field is only writable when the SAFE_MODE bit is cleared to 0, and
SAFE_MODE is only cleared by PWROK rising edge. These bits are in the RTC well.
Secondary Reset State (SRS) — R/W.
reset.
feature space).
same timings as the other CPU I/F signals (Hold Time after CPURST# inactive). Note that
CPURST# is generated by the memory controller hub, but the ICH4 has a hub interface special
cycle that allows the ICH4 to control the assertion/deassertion of CPURST#.
writes.
D5h
CFh
(upon RTCRST# assertion low)
EFh
(if Safe Mode Strap is active)
No
Description
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W
8 bit
RTC
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