FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 433

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

11.2.5
Intel
®
82801DBM ICH4-M Datasheet
FRBASEADD—Frame List Base Address
I/O Offset:
Default Value:
This 32-bit register contains the beginning address of the Frame List in the system memory. HCD
loads this register prior to starting the schedule execution by the Host Controller. When written,
only the upper 20 bits are used. The lower 12 bits are written as 0s (4-kB alignment). The contents
of this register are combined with the frame number counter to enable the Host Controller to step
through the Frame List in sequence. The two least significant bits are always 00. This requires
DWord alignment for all list entries. This configuration supports 1024 Frame List entries.
31:12
11:0
Bit
Base Address — R/W. These bits correspond to memory address signals [31:12], respectively.
Reserved
Base + (08
Undefined
–
0Bh)
Description
Attribute:
Size:
USB UHCI Controllers Registers
R/W
32 bits
433