FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 87

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.2.2.5
Intel
®
82801DBM ICH4-M Datasheet
PCI Reset Signal
The PCIRST# signal may be activated in one of the following cases:
If PME# is enabled (in the PCI power management registers), PCIRST# assertion does not affect
any PME# related circuits (in other words, PCI power management registers and the wake-up
packet would not be affected). While PCIRST# is active, the LAN Controller ignores other PCI
signals. The configuration of the LAN Controller registers associated with ACPI wake events is not
affected by PCIRST#.
The integrated LAN Controller uses the PCIRST# or the PWROK signal as an indication to ignore
the PCI interface. Following the deassertion of PCIRST#, the LAN Controller PCI Configuration
Space, MAC configuration, and memory structure are initialized while preserving the PME# signal
and its context.
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D1 Power State
In order for a device to meet the D1 power state requirements, as specified in the Advanced
Configuration and Power Interface (ACPI) Specification, Revision 2.0, it must not allow bus
transmission or interrupts; however, bus reception is allowed. Therefore, device context may
be lost and the LAN Controller does not initiate any PCI activity. In this state, the LAN
Controller responds only to PCI accesses to its configuration space and system wake-up
events.
The LAN Controller retains link integrity and monitors the link for any wake-up events (e.g.,
wake-up packets or link status chang)e. Following a wake-up event, the LAN Controller
asserts the PME# signal.
D2 Power State
The ACPI D2 power state is similar in functionality to the D1 power state. In addition to D1
functionality, the LAN Controller can provide a lower power mode with wake-on-link status
change capability. The LAN Controller may enter this mode if the link is down while the LAN
Controller is in the D2 state. In this state, the LAN Controller monitors the link for a transition
from an invalid to a valid link.
The sub,10-mA state due to an invalid link can be enabled or disabled by a configuration bit in
the Power Management Driver Register (PMDR). The LAN Controller will consume in D2
<10 mA, regardless of the link status. It is the LAN Connect component that consumes much
less power during link down, hence LAN Controller in this state can consume <10 mA.
D3 Power State
In the D3 power state, the LAN Controller has the same capabilities and consumes the same
amount of power as it does in the D2 state. However, it enables the PCI system to be in the B3
state. If the PCI system is in the B3 state (in other words, no PCI power is present), the LAN
Controller provides wake-up capabilities. If PME is disabled, the LAN Controller does not
provide wake-up capability or maintain link integrity. In this mode the LAN Controller
consumes its minimal power.
The LAN Controller enables a system to be in a sub-5 watt state (low power state) and still be
virtually connected. More specifically, the LAN Controller supports full wake-up capabilities
while it is in the D3 cold state. The LAN Controller is in the ICH4 resume well, and thus is
connected to an auxiliary power source (V AUX), which enables it to provide wake-up
functionality while the PCI power is off.
During S3–S5 states
Due to a CF9h reset
Functional Description
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