FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 27

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
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82801DBM ICH4-M Datasheet
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Short Message.............................................................................................123
APIC Bus Status Cycle Definition ................................................................124
Lowest Priority Message (Without Focus Processor) ..................................125
Remote Read Message ...............................................................................126
Interrupt Message Address Format .............................................................129
Interrupt Message Data Format ...................................................................130
Stop Frame Explanation ..............................................................................131
Data Frame Format......................................................................................132
Configuration Bits Reset By RTCRST# Assertion .......................................135
INIT# Going Active.......................................................................................137
NMI Sources ................................................................................................138
Frequency Strap Behavior Based on Exit State...........................................139
Frequency Strap Bit Mapping ......................................................................139
General Power States for Systems Using Intel
State Transition Rules for Intel
System Power Plane....................................................................................143
Causes of SMI# and SCI .............................................................................144
Break Events................................................................................................146
Sleep Types .................................................................................................151
Causes of Wake Events...............................................................................152
GPI Wake Events.........................................................................................152
Transitions Due to Power Failure.................................................................153
Transitions Due to Power Button .................................................................157
Transitions Due to RI# Signal ......................................................................158
Write Only Registers with Read Paths in ALT Access Mode.......................160
PIC Reserved Bits Return Values................................................................162
Register Write Accesses in ALT Access Mode............................................163
Intel ICH4 Clock Inputs ................................................................................165
Alert on LAN* Message Data .......................................................................171
GPIO Implementation ..................................................................................173
IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select) .....176
IDE Legacy I/O Ports: Control Block Registers (CS3x# Chip Select) ..........176
Interrupt/Active Bit Interaction Definition......................................................182
UltraATA/33 Control Signal Redefinitions ....................................................183
Frame List Pointer Bit Description ...............................................................186
TD Link Pointer ............................................................................................187
TD Control and Status .................................................................................188
TD Token .....................................................................................................190
TD Buffer Pointer .........................................................................................190
Queue Head Block.......................................................................................191
Queue Head Link Pointer.............................................................................191
Queue Element Link Pointer ........................................................................191
Command Register, Status Register, and TD Status Bit Interaction ...........194
Queue Advance Criteria...............................................................................196
USB Schedule List Traversal Decision Table ..............................................197
PID Format...................................................................................................199
PID Types ....................................................................................................199
Address Field ...............................................................................................200
Endpoint Field ..............................................................................................200
Token Format...............................................................................................201
IDE Transaction Timings (PCI Clocks) .......................................................177
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ICH4 .........................................................142
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ICH4 ................................141
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