FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 420

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

USB UHCI Controllers Registers
11.1.2
11.1.3
420
DID—Device Identification Register (USB—D29:F0/F1/F2)
Address Offset:
Default Value:
CMD—Command Register (USB—D29:F0/F1/F2)
Address Offset:
Default Value:
15:10
15:0
Bit
Bit
9
8
7
6
5
4
3
2
1
0
Device Identification Value — RO . This is a 16-bit value assigned to the ICH4 USB Host
Controllers.
Reserved
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — RO. Reserved as 0.
VGA Palette Snoop (VSP) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — RW. When set, the ICH4 can act as a master on the PCI bus for USB
transfers.
Memory Space Enable (MSE) — RO. Reserved as 0.
I/O Space Enable (IOSE) — RW. This bit controls access to the I/O space registers.
0 = Disable
1 = Enable accesses to the USB I/O registers. The Base Address register for USB should be
programmed before this bit is set.
02
Function 0: 24C2h
Function 1: 24C4h
Function 2: 24C7h
04
0000h
–
–
03h
05h
Description
Description
Attribute:
Size:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
RO
16 bits
R/W, RO
16 bits