FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 234

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.18.1.2
234
Table 5-89. I
Note: When operating in I
For I
I/O register, offset 04h) needs to be 0. The format that is used for the new command is shown in
Table
The ICH4 will continue reading data from the peripheral until the NAK is received.
I
When the I
devices. This forces the following changes:
In addition, the ICH4 will support the new I
bit.
2
•
•
C Behavior
2
C Block Read
The Process Call command will skip the Command code (and its associated acknowledge)
The Block Write command will skip sending the Byte Count (DATA0)
2
C Read command, the value written into bit 0 of the Transmit Slave Address Register (SMB
5-89.
20–27
29–36
39–45
48–55
57–64
11–18
2–8
Bit
10
19
28
37
38
46
47
56
65
—
—
—
—
1
9
2
C_EN bit is set, the ICH4 SMBus logic will instead be set to communicate with I
2
C mode the ICH4 will not use the 32-byte buffer for block commands.
Start
Slave Address - 7 bits
Write
Acknowledge from slave
Command code - 8 bits
Acknowledge from slave
Send DATA0 register
Acknowledge from slave
Send DATA1 register
Acknowledge from slave
Repeated start
Slave Address - 7 bits
Read
Acknowledge from slave
Data byte from slave
Acknowledge
Data byte 2 from slave - 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data byte N from slave - 8 bits
NOT Acknowledge
Stop
Description
2
C Read command. This is independent of the I
Intel
®
82801DBM ICH4-M Datasheet
2
C_EN
2
C