FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 479

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801DBM ICH4-M Datasheet
Bit
6
5
4
3
2
1
0
INUSE_STS — R/WC (special). This bit is used as semaphore among various independent
software threads that may need to use the ICH4’s SMBus logic, and has no other effect on
hardware.
0 = After a full PCI reset, a read to this bit returns a 0.
1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next
SMBALERT_STS — R/WC. If the signal is programmed as a GPIO, then this bit will never be set.
0 = Interrupt or SMI# was not generated by SMBALERT#. This bit is only cleared by software
1 = The source of the interrupt or SMI# was the SMBALERT# signal.
FAILED — R/WC.
0 = Cleared by writing a 1 to the bit position.
1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in response to
BUS_ERR — R/WC.
0 = Cleared by writing a 1 to the bit position.
1 = The source of the interrupt of SMI# was a transaction collision.
DEV_ERR — R/WC.
0 = Software resets this bit by writing a 1 to this location. The ICH4 will then deassert the interrupt
1 = The source of the interrupt or SMI# was due to one of the following:
INTR — R/WC (special). This bit can only be set by termination of a command. INTR is not
dependent on the INTREN bit of the Host Controller Register (offset 02h). It is only dependent on
the termination of the command. If the INTREN bit is not set, then the INTR bit will be set, although
the interrupt will not be generated. Software can poll the INTR bit in this non-interrupt case.
0 = Software resets this bit by writing 1 to this location. The ICH4 will then deassert the interrupt or
1 = The source of the interrupt or SMI# was the successful completion of its last command.
HOST_BUSY — RO.
0 = Cleared by the ICH4 when the current transaction is completed.
1 = Indicates that the ICH4 is running a command from the host interface. No SMB registers should
read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0,
and will then own the usage of the host controller.
writing a 1 to the bit position or by RSMRST# going low.
the KILL bit being set to terminate the host transaction.
or SMI#.
SMI#.
be accessed while this bit is set, except the BLOCK DATA BYTE Register. The BLOCK DATA
BYTE Register can be accessed when this bit is set only when the SMB_CMD bits in the Host
Control Register are programmed for Block command or I
necessary in order to check the DONE_STS bit.
•Illegal Command Field,
•Unclaimed Cycle (host initiated),
•Host Device Time-out Error.
Description
SMBus Controller Registers (D31:F3)
2
C Read command. This is
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