FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 313

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.1.17
9.1.18
Intel
®
82801DBM ICH4-M Datasheet
SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
5:2
1:0
Bit
Bit
6:4
3:0
7
6
7
Serial IRQ Enable (SIRQEN) — R/W.
0 = The buffer is input only and internally SERIRQ will be a 1.
1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ.
Serial IRQ Mode Select (SIRQMD) — R/W.
0 = The serial IRQ machine will be in quiet mode.
1 = The serial IRQ machine will be in continuous mode.
NOTE: For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for at least one
Serial IRQ Frame Size (SIRQSZ) — R/W. Fixed field that indicates the size of the SERIRQ frame. In
the ICH4, this field needs to be programmed to 21 frames (0100). This is an offset from a base of 17
which is the smallest data frame size.
Start Frame Pulse Width (SFPW) — R/W. This is the number of PCI clocks that the SERIRQ pin will
be driven low by the serial IRQ machine to signal a start frame. In continuous mode, the ICH4 will
drive the start frame for the number of clocks specified. In quiet mode, the ICH4 will drive the start
frame for the number of clocks specified minus one, as the first clock was driven by the peripheral.
00 = 4 clocks
01 = 6 clocks
10 = 8 clocks
11 = Reserved
Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The
Reserved
IRQ Routing — R/W. (ISA compatible)
0000 = Reserved1000 = Reserved
0001 = Reserved1001 = IRQ9
0010 = Reserved1010 = IRQ10
0011 = IRQ31011 = IRQ11
0100 = IRQ41100 = IRQ12
0101 = IRQ51101 = Reserved
0110 = IRQ61110 = IRQ14
0111 = IRQ71111 = IRQ15
frame after coming out of reset before switching back to Quiet Mode. Failure to do so will
result in the ICH4 not recognizing SERIRQ interrupts.
value of this bit may subsequently be changed by the OS when setting up for I/O APIC
interrupt delivery mode.
64h
10h
No
PIRQE–68h, PIRQF–69h,
PIRQG–6Ah, PIRQH–6Bh
80h
No
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W
8 bit
Core
R/W
8 bit
Core
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