FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 237

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.18.5
5.18.6
5.18.7
Intel
®
82801DBM ICH4-M Datasheet
Note: Any event on SMBALERT# (regardless whether it is programmed as a GPIO or not), causes the
Note: When an external micro controller accesses the SMBus Slave Interface over the SMLink a
SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enable and the signal is asserted, The ICH4
can generate an interrupt, an SMI# or a wake event from S1-M–S5.
event message to be sent in “heartbeat mode.”
SMBus CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, the ICH4 automatically calculates and drives
CRC at the end of the transmitted packet for write cycles and checks the CRC for read cycles. It
will not transmit the contents of the PEC register for CRC. The PEC bit must not be set in the Host
Control register if this bit is set, or unspecified behavior will result.
If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the Auxiliary Status
register at offset 0Ch will be set.
SMBus Slave Interface
The ICH4’s SMBus Slave interface is accessed via the SMLINK[1:0] signals. The SMBus slave
logic does not generate or handle receiving the PEC byte and only acts as a Legacy Alerting
Protocol (Alert on LAN*) device. The slave interface allows the ICH4 to decode cycles, and allows
an external microcontroller to perform specific actions. Key features and capabilities include:
If a master leaves the clock and data bits of the SMLink interface at 1 for 50 µs or more in the
middle of a cycle, the ICH4 slave logic's behavior is undefined. This is interpreted as an
unexpected idle and should be avoided when performing management activities to the slave logic.
translation in the address is needed to accommodate the least significant bit used for read/write
control. For example, if the ICH4 slave address (RCV_SLVA) is left at 44h (default), the external
microcontroller would use an address of 88h/89h (write/read).
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Supports decode of three types of messages: Byte Write, Byte Read, and Host Notify
Receive Slave Address register: This is the address that the ICH4 decodes. A default value is
provided so that the slave interface can be used without the processor having to program this
register.
Receive Slave Data register in the SMBus I/O space that includes the data written by the
external microcontroller
Registers that the external microcontroller can read to get the state of the ICH4. See
Status bits to indicate that the SMLink/SMBus slave logic caused an interrupt or SMI# due to
the reception of a message that matched the slave address.
— Bit 0 of the Slave Status Register for the Host Notify command
— Bit 16 of the SMI Status Register
(Section
9.8.3.13) for all others
Functional Description
Table 5-97
237