FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 312

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.1.14
9.1.15
9.1.16
312
GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
31:16
15:6
Bit
7:5
3:0
Bit
6:4
3:0
Bit
5:1
4
7
0
Reserved
GPIO Enable (GPIO_EN) — R/W. This bit enables/disables decode of the I/O range pointed to by
the GPIO base register and enables/disables the GPIO function.
0 = Disable.
1 = Enable.
Reserved
Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The
Reserved
IRQ Routing — R/W. (ISA compatible)
0000 = Reserved1000 = Reserved
0001 = Reserved1001 = IRQ9
0010 = Reserved1010 = IRQ10
0011 = IRQ31011 = IRQ11
0100 = IRQ41100 = IRQ12
0101 = IRQ51101 = Reserved
0110 = IRQ61110 = IRQ14
0111 = IRQ71111 = IRQ15
Reserved
Base Address — R/W. Provides the 64 bytes of I/O space for GPIO.
Reserved
Resource Indicator — RO. Hardwired to 1; indicates I/O space.
value of this bit may subsequently be changed by the OS when setting up for I/O APIC
interrupt delivery mode.
58h
00000001h
PIRQA–60h, PIRQB–61h,
No
5Ch
00h
No
PIRQC–62h, PIRQD–63h
80h
No
–
5Bh
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Intel
®
82801DBM ICH4-M Datasheet
R/W, RO
32 bit
Core
R/W
8 bit
Core
R/W
8 bit
Core