FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 151

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.12.7.2
5.12.7.3
Intel
®
Table 5-39. Sleep Types
82801DBM ICH4-M Datasheet
Note: If the BATLOW# signal is asserted, ICH4 will not attempt to wake from an S1-M–S5 state, even if
Initiating Sleep State
Sleep states (S1-M–S5) are initiated by:
Exiting Sleep States
Sleep states (S1-M–S5) are exited based on Wake events. The Wake events force the system to a
full on state (S0), although some non-critical subsystems might still be shut off and have to be
brought back manually. For example, the hard disk may be shut off during a sleep state, and have to
be enabled via a GPIO pin before it can be used.
Upon exit from the ICH4-controlled Sleep states, the WAK_STS bit is set. The possible causes of
Wake Events (and their restrictions) are shown in
the power button is pressed. This prevents the system from waking when the battery power is
insufficient to wake the system. Wake events that occur while BATLOW# is asserted will be
latched by the ICH4, and the system will wake after BATLOW# is deasserted.
Sleep Type
•
•
S1-M
Masking interrupts, turning off all bus master enable bits, setting the desired type in the
SLP_TYP field, and then setting the SLP_EN bit. The hardware will then attempt to gracefully
put the system into the corresponding Sleep state by first going to a C2 or C3 state. See
Section 5.12.5
Pressing the PWRBTN# signal for more than 4 seconds to cause a Power Button Override
event. In this case the transition to the S5 state will be less graceful, since there will be no
dependencies on observing Stop-Grant cycles from the processor or on clocks other than the
RTC clock.
S3
S4
S5
ICH4 asserts the SLP_S1# signal. This can be connected to the system clock generator to
either put it into a low-power mode or to remove its power altogether. No snooping is possible
in this state.
NOTE: Ability to assert DPRSLPVR and DPSLP# within S1-M to enter “Deeper Sleep”.
NOTE: ICH4-M requires that the I/O APIC interrupts be masked before entering S1-M. If
ICH4 asserts SLP_S1# and SLP_S3#. The SLP_S3# signal will control the power to non-
critical circuits. Power will only be retained to devices needed to wake from this sleeping state,
as well as to the memory.
ICH4 asserts SLP_S1#, SLP_S3#, and SLP_S4#. The SLP_S4# signal will shut off the power
to the memory subsystem. Only devices needed to wake from this state should be powered.
Same power state as S4. ICH4 asserts SLP_S1#, SLP_S3#, SLP_S4# and SLP_S5#.
for details on going to the C2 or C3 state.
software does not mask all interrupts in I/O APIC prior to entering S1-M, the system
may hang during resume from S1-M.
Table
Comment
5-40.
Functional Description
151