FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 246

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
246
Table 5-100. AC ’97 Signals
Figure 5-23. AC-Link Protocol
The AC-link consists of a five signal interface between the controller and codec.
indicates the AC-link signal pins on the ICH4 and their associated power wells.
NOTE: Power well voltage levels are 3.3 V.
ICH4 core well outputs may be used as strapping options for the ICH4, sampled during system
reset. These signals may have weak pullups/pulldowns on them, however this will not interfere
with link operation. ICH4 inputs integrate weak pulldowns to prevent floating traces when a
secondary and/or tertiary codec is not attached. When the Shut Off bit in the control register is set,
all buffers will be turned off and the pins will be held in a steady state, based on these pullups/
pulldowns.
AC_BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides the
necessary clocking to support the twelve 20-bit time slots. AC-link serial data is transitioned on
each rising edge of AC_BIT_CLK. The receiver of AC-link data samples each serial bit on the
falling edge of AC_BIT_CLK.
If AC_BIT_CLK makes no transitions for four consecutive PCI clocks, the ICH4 assumes the
primary codec is not present or not working. It sets bit 28 of the Global Status Register (I/O offset
30h). All accesses to codec registers with this bit set will return data of FFh to prevent system
hangs.
Synchronization of all AC-link data transactions is signaled by the Af97 controller via the
AC_SYNC signal, as shown in
AC-link, which the AC ’97 controller then qualifies with the AC_SYNC signal to construct data
frames. AC_SYNC, fixed at 48 kHz, is derived by dividing down AC_BIT_CLK. AC_SYNC
remains high for a total duration of 16 AC_BIT_CLKs at the beginning of each frame. The portion
of the frame where AC_SYNC is high is defined as the tag phase. The remainder of the frame
where AC_SYNC is low is defined as the data phase. Each data bit is sampled on the falling edge
of AC_BIT_CLK.
AC_RST#
AC_SYNC
AC_BIT_CLK
AC_SDOUT
AC_SDIN 0
AC_SDIN 1
AC_SDIN 2
Signal Name
BIT_CLK
SDIN
SYNC
End of previous
Audio Frame
Codec
Ready
12.288 MHz
slot(1)
("1" = time slot contains valid PCM
Output
Output
Output
Type
Input
Input
Input
Input
Tag Phase
slot(2)
81.4 nS
Time Slot "Valid"
slot(12)
Figure
Bits
"0"
Power Well
5-23. The primary codec drives the serial bit clock onto the
Resume
Resume
Resume
Resume
"0"
Core
Core
Core
"0"
19
Slot 1
Master hardware reset
48 kHz fixed rate sample sync
12.288 MHz Serial data clock
Serial output data
Serial input data
Serial input data
Serial input data
0
(48 KHz)
20.8uS
19
Slot 2
Data Phase
Intel
Description
0
®
82801DBM ICH4-M Datasheet
19
Slot 3
0
Table 5-100
19
Slot 12
0