FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 484

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

SMBus Controller Registers (D31:F3)
13.2.12
.
13.2.13
484
Note: This register is in the resume well and is reset by RSMRST#.
AUX_CTL—Auxiliary Control Register
Register Offset:
Default Value:
Lockable:
SMLINK_PIN_CTL—SMLink Pin Control Register
Register Offset:
Default Value:
Bit
7:2
7:3
Bit
1
0
2
1
0
Reserved
Enable 32-byte Buffer (E32B) — R/W.
0 = Disable.
1 = Enable. The Host Block Data register is a pointer into a 32-byte buffer, as opposed to a single
Automatically Append CRC (AAC) — R/W.
0 = Disable.
1 = Enable. The ICH4 automatically appends the CRC. This bit must not be changed during SMBus
Reserved
SMLINK_CLK_CTL — R/W.
0 = ICH4 drives the SMLINK[0] pin low, independent of what the other SMLINK logic would otherwise
1 = The SMLINK[0] pin is not overdriven low. The other SMLINK logic controls the state of the pin.
SMLINK1_CUR_STS — R/W. This pin returns the value on the SMLINK[1] pin. This allows software
to read the current state of the pin. Default value is dependent on an external signal level.
0 = Low
1 = High
SMLINK0_CUR_STS — RO. This pin returns the value on the SMLINK[0] pin. This allows software to
read the current state of the pin. Default value is dependent on an external signal level.
0 = Low
1 = High
register. This enables the block commands to transfer or receive up to 32-bytes before the ICH4
generates an interrupt.
transactions, or undetermined behavior will result
indicate for the SMLINK[0] pin.
(Default)
No
0Eh
0Dh
00h
See below
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/W
8 bits
Resume
R/W, RO
8 bits