FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 387

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.8.3.19
9.8.3.20
Intel
®
82801DBM ICH4-M Datasheet
BUS_ADDR_TRACK— Bus Address Tracker
I/O Address:
Lockable:
Power Well:
This register could be used by the SMI# handler to assist in determining what was the last cycle
from the processor. BUS_ADDR_TRACK may not contain “expected” last I/O cycle data if
Asynchronous SMIs and Synchronous SMIs are occurring simultaneously. This register only
reports “expected” last I/O cycle data if Asynchronous SMIs are disabled.
BUS_CYC_TRACK— Bus Cycle Tracker
I/O Address:
Lockable:
Power Well:
This register could be used by the SMM handler to assist in determining what was the last cycle
from the CPU. BUS_CYC_TRACK may not contain “expected” last I/O cycle data if
Asynchronous SMIs and Synchronous SMIs are occurring simultaneously. This register only
reports “expected” last I/O cycle data if Asynchronous SMIs are disabled.
15:0
Bit
Bit
Bit
7:4
3:0
0
IDEP0_TRP_EN — R/W. IDE Primary Drive 0.
0 = Disable.
1 = Enable.
Corresponds to the low 16 bits of the last I/O cycle, as would be defined by the PCI AD[15:0] signals
on the PCI bus (even though it may not be a real PCI cycle). The value is latched based on SMI#
active. This functionality is useful for figuring out which I/O was last being accessed.
Corresponds to the byte enables, as would be defined by the PCI C/BE# signals on the PCI bus
(even though it may not be a real PCI cycle). The value is latched based on SMI# going active.
Corresponds to the cycle type, as would be defined by the PCI C/BE# signals on the PCI bus (even
though it may not be a real PCI cycle). The value is latched based on SMI# going active.
PMBASE +4Ch
No
Core
PMBASE +4Eh
No
Core
Description
Description
Description
Attribute:
Size:
Usage:
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
RO
16 bit
Legacy Only
RO
8 bit
Legacy Only
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