FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 487

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

13.2.18
13.2.19
Intel
®
82801DBM ICH4-M Datasheet
Note: This register is in the resume well and is reset by RSMRST#
Note: This register is in the resume well and is reset by RSMRST#
NOTIFY_DLOW—Notify Data Low Byte Register
Register Offset:
Default Value:
NOTIFY_DHIGH—Notify Data High Byte Register
Register Offset:
Default Value:
7:0
7:0
Bit
Bit
DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received during the Host
Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when the
HOST_NOTIFY_STS bit is set to 1.
DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received during the Host
Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when the
HOST_NOTIFY_STS bit is set to 1.
16h
00h
17h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
SMBus Controller Registers (D31:F3)
RO
8 bits
RO
8 bits
487