FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 282

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LAN Controller Registers (B1:D8:F0)
7.2.6
282
Management Data Interface (MDI) Control Register
Offset Address:
Default Value:
The Management Data Interface (MDI) Control register is a 32-bit field and is used to read and
write bits from the LAN Connect component. This register may be written as a 32-bit entity, two
16-bit entities, or four 8-bit entities. The LAN Controller will only accept the command after the
high byte (offset 13h) is written, therefore the high byte must be written last.
31:30
27:26
25:21
20:16
15:0
Bit
29
28
These bits are reserved and should be set to 00b.
Interrupt Enable — R/W.
0 = Disable.
1 = Enables the LAN Controller to assert an interrupt to indicate the end of an MDI cycle.
Ready — R/W.
0 = Expected to be reset by software at the same time the command is written.
1 = Set by the LAN Controller at the end of an MDI transaction.
Opcode — R/W. These bits define the opcode:
00 = Reserved
01 = MDI write
10 = MDI read
11 = Reserved
LAN Connect Address — R/W. This field of bits contains the LAN Connect address.
LAN Connect Register Address — R/W. This field of bits contains the LAN Connect Register
Address.
Data — R/W. In a write command, software places the data bits in this field, and the LAN* Controller
transfers the data to the external LAN Connect component. During a read command, the LAN
Controller reads these bits serially from the LAN Connect, and software reads the data from this
location.
10
0000 0000h
–
13h
Description
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/W (special)
32 bits