FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 292

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.4
292
PD_STS—Primary Device Status Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit will have no
effect.
10:9
Bit
4:0
15
14
13
12
11
8
7
6
5
Detected Parity Error (DPE) — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = Indicates that the ICH4 detected a parity error on the hub interface. This bit gets set even if the
Signaled System Error (SSE)
0 = Software clears this bit by writing a 1 to the bit location.
1 = An address, or command parity error, or special cycles data parity error has been detected on
Received Master Abort (RMA) — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = ICH4 received a master abort from the hub interface device.
Received Target Abort (RTA) — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = ICH4 received a target abort from the hub interface device. The TCO logic can cause an SMI#,
Signaled Target Abort (STA) — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = ICH4 signals a target abort condition on the hub interface.
DEVSEL# Timing Status (DEV_STS) — RO.
00h = Fast timing. This register applies to the hub interface; therefore, this field does not matter.
Master Data Parity Error Detected (MDPD) — R/WC. Since this register applies to the hub
interface, the ICH4 must interpret this bit differently than it is in the PCI spec.
0 = Software clears this bit by writing a 1 to the bit location.
1 = ICH4 detects a parity error on the hub interface and the Parity Error Response bit in the
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Reserved
Parity Error Response bit (offset 04, bit 6) is not set.
the PCI bus, and the Parity Error Response bit (D30:F0, Offset 04h, bit 6) is set. If this bit is set
because of parity error and the D30:F0 SERR_EN bit (Offset 04h, bit 8) is also set, the ICH4
will generate an NMI (or SMI# if NMI routed to SMI#).
NMI, or interrupt based on this bit getting set.
Command Register (offset 04h, bit 6) is set.
06
0080h
–
07h
—
R/WC.
Description
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/WC, RO
16 bits