FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 397

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.10.1
9.10.2
Intel
®
82801DBM ICH4-M Datasheet
GPIO_USE_SEL—GPIO Use Select Register
Offset Address:
Default Value:
Lockable:
GP_IO_SEL—GPIO Input/Output Select Register
Offset Address:
Default Value:
Lockable:
21,11,
31:29, 26
5:0
Bit
24:18,
28:27
17:16
15:0
Bit
25
GPIO_USE_SEL — R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be
used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
1. . Bits 31:29, 26, 24:18,15:14, 10:9, and 6 are not implemented because there is no
2. Bits 28:27, 25, 13:12 and 8:7 are not implemented because the corresponding GPIOs are not
1. Bits 16:17 are not implemented because the GPIO selection is controlled by bits 0:1. The REQ/
corresponding GPIO.
multiplexed.
GNT# pairs are enabled/disabled together. For example, if bit 0 is set to 1, then the REQ/
GNT[A]# pair will function as GPIO[0] and GPIO[16].
Reserved
GPIO[n]_SEL — R/W.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
Reserved
Always 0. The GPIOs are fixed as outputs.
Always 1. These GPIOs are fixed as inputs.
NOTE: Bits 15:14, 10:9, 6 are not implemented and are reserved.
GPIOBASE + 00h
1A003180h
Yes
GPIOBASE +04h
0000FFFFh
No
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
32-bit
Resume
R/W
32-bit
Resume
R/W
397