FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 270

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LAN Controller Registers (B1:D8:F0)
7.1.9
7.1.10
7.1.11
270
Note: The ICH4’s integrated LAN Controller requires one BAR for memory mapping. Software
PMLT—PCI Master Latency Timer Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
HEADTYP—Header Type Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
CSR_MEM_BASE CSR — Memory-Mapped Base Address
Register (LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
determines which BAR (memory or I/O) is used to access the Lan Controller’s CSR registers.
31:12
11:4
7:3
2:0
6:0
2:1
Bit
Bit
Bit
7
3
0
Master Latency Timer Count (MLTC) — R/W. Defines the number of PCI clock cycles that the
integrated LAN Controller may own the bus while acting as bus master.
Reserved
Multi-Function Device — RO. Hardwired to 0 to indicate a single function device.
Header Type — RO. This 7-bit field identifies the header layout of the configuration space as an
Ethernet controller.
Base Address — R/W. Upper 20 bits of the base address provides 4 KB of memory-Mapped space
for the LAN* Controller’s Control/Status Registers.
Reserved
Prefetchable — RO. Hardwired to 0 to indicate that this is not a pre-fetchable memory-Mapped
address range.
Type — RO. Hardwired to 00b to indicate the memory-Mapped address range may be located
anywhere in 32-bit address space.
Memory Space Indicator — RO. Hardwired to 0 to indicate that this base address maps to memory
space.
10
0000 0008h
0Dh
00h
0Eh
00h
–
13h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/W
8 bits
RO
8 bits
R/W, RO
32 bits