FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 73

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5
5.1
5.1.1
Intel
®
82801DBM ICH4-M Datasheet
Note: The ICH4’s AC ’97, IDE and USB Controllers cannot perform peer-to-peer traffic.
Note: Devices on the ICH4 PCI bus (other than the ICH4) are not permitted to assert the PLOCK# signal.
Note: Poor performing PCI devices that cause long latencies (numerous retries) to processor-to-PCI
Note: PCI configuration write cycles, initiated by the processor, with the following characteristics will be
This chapter describes the functions and interfaces of the ICH4.
Hub Interface to PCI Bridge (D30:F0)
The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the
ICH4 implements the buffering and control logic between PCI and the hub interface. The
arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must
decode the ranges for the hub interface. All register contents will be lost when core well power is
removed.
PCI Bus Interface
The ICH4 PCI interface provides a 33-MHz, PCI Local Bus Specification, Revision 2.2-compliant
implementation. All PCI signals are 5-V tolerant. The ICH4 integrates a PCI arbiter that supports
up to six external PCI bus masters in addition to the internal ICH4 requests.
Note that most transactions targeted to the ICH4 will first appear on the external PCI bus before
being claimed back by the ICH4. The exceptions are I/O cycles involving USB, IDE, and AC ’97.
These transactions will complete over the hub interface without appearing on the external PCI bus.
Configuration cycles targeting USB, IDE, or AC ’97 will appear on the PCI bus. If the ICH4 is
programmed for positive decode, the ICH4 will claim the cycles appearing on the external PCI bus
in medium decode time. If the ICH4 is programmed for subtractive decode, the ICH4 will claim
these cycles in subtractive time. If the ICH4 is programmed for subtractive decode, these cycles
can be claimed by another positive decode agent out on PCI. This architecture enables the ability to
boot off of a PCI card that positively decodes the boot cycles. In order to boot off a PCI card it is
necessary to keep the ICH4 in subtractive decode mode. When booting off a PCI card, the
BOOT_STS bit (bit 2, TCO2 Status Register) will be set.
Locked cycles may starve isochronous transfers between USB or AC ’97 devices and memory.
This will result in overrun or underrun, causing reduced quality of the isochronous data
(e.g., audio).
converted to a Special Cycle with the Shutdown message type.
Functional Description
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Device Number (AD[15:11]) = 11111
Function Number (AD[10:8]) = 111
Register Number (AD[7:2]) = 000000
Data = 00h
Bus number matches secondary bus number
Functional Description
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