FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 599

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Table A-2. Intel
Intel
Channel 0 DMA Base & Current
Address Register
Channel 0 DMA Base & Current
Count Register
Channel 0 DMA Memory Low Page
Register
Channel 0–3 DMA Command
Register
Channel 0–3 DMA Status Register
Channel 0–3 DMA Write Single
Mask Register
Channel 0–3 DMA Channel Mode
Register
Channel 0–3 DMA Clear Byte
Pointer Register
Channel 0–3 DMA Master Clear
Register
Channel 0–3 DMA Clear Mask
Register
Channel 0–3 DMA Write All Mask
Register
Timer Control Word Register
Timer Control Word Register Read
Back
Counter Latch Command
Interval Timer Status Byte Format
Counter Access Port Register
Initialization Command Word 1
Register
Initialization Command Word 2
Register
Master Controller Initialization
Command Word 3 Register
Slave Controller Initialization
Command Word 3 Register
Initialization Command Word 4
Register
Operational Control Word 1
Register
Operational Control Word 2
Register
®
82801DBM ICH4-M Datasheet
Register Name
®
ICH4 Fixed I/O Registers (Sheet 1 of 2)
Port
0Ch
0Dh
00h
01h
87h
08h
08h
0Ah
0Bh
0Eh
0Fh
43h
40h
40h
20h
21h
21h
A1h
21h
21h
20h
8254 Interrupt Controller
Timer I/O Registers
Section 9.2.1, “DMABASE_CA—DMA Base and Current Address
Registers” on page 9-331
Section 9.2.2, “DMABASE_CC—DMA Base and Current Count Registers”
on page 9-331
Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page Registers” on
page 9-332
Section 9.2.4, “DMACMD—DMA Command Register” on page 9-332
Section 9.2.5, “DMASTA—DMA Status Register” on page 9-333
Section 9.2.6, “DMA_WRSMSK—DMA Write Single Mask Register” on
page 9-333
Section 9.2.7, “DMACH_MODE—DMA Channel Mode Register” on
page 9-334
Section 9.2.8, “DMA Clear Byte Pointer Register” on page 9-334
Section 9.2.9, “DMA Master Clear Register” on page 9-335
Section 9.2.10, “DMA_CLMSK—DMA Clear Mask Register” on
page 9-335
Section 9.2.11, “DMA_WRMSK—DMA Write All Mask Register” on
page 9-335
Section 9.3.1, “TCW—Timer Control Word Register” on page 9-336
Section 9.3.1.1, “RDBK_CMD—Read Back Command” on page 9-337
Section 9.3.1.2, “LTCH_CMD—Counter Latch Command” on page 9-337
Section 9.3.2, “SBYTE_FMT—Interval Timer Status Byte Format Register”
on page 9-338
Section 9.3.3, “Counter Access Ports Register” on page 9-338
Section 9.4.1, “ICW1—Initialization Command Word 1 Register” on
page 9-340
Section 9.4.2, “ICW2—Initialization Command Word 2 Register” on
page 9-341
Section 9.4.3, “ICW3—Master Controller Initialization Command Word 3
Register” on page 9-341
Section 9.4.4, “ICW3—Slave Controller Initialization Command Word 3
Register” on page 9-342
Section 9.4.5, “ICW4—Initialization Command Word 4 Register” on
page 9-342
Section 9.4.6, “OCW1—Operational Control Word 1 (Interrupt Mask)
Register” on page 9-342
Section 9.4.7, “OCW2—Operational Control Word 2 Register” on
page 9-343
DMA I/O Registers
Datasheet Location
Register Index
599