FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 115

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.7.2.2
5.7.2.3
5.7.2.4
5.7.3
5.7.4
5.7.4.1
Intel
®
82801DBM ICH4-M Datasheet
ICW2
The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the interrupt
vector that will be released during an interrupt acknowledge. A different base is selected for each
interrupt controller.
ICW3
The third write in the sequence (ICW3) has a different meaning for each controller.
ICW4
The final write in the sequence, ICW4, must be programmed both controllers. At the very least,
bit 0 must be set to a 1 to indicate that the controllers are operating in an Intel Architecture-based
system.
Operation Command Words (OCW)
These command words reprogram the Interrupt Controller to operate in various interrupt modes.
Modes of Operation
Fully Nested Mode
In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest.
When an interrupt is acknowledged, the highest priority request is determined and its vector placed
on the bus. Additionally, the ISR for the interrupt is set. This ISR bit remains set until: the
processor issues an EOI command immediately before returning from the service routine; or if in
AEOI mode, on the trailing edge of the second INTA#. While the ISR bit is set, all further
interrupts of the same or lower priority are inhibited, while higher levels will generate another
interrupt. Interrupt priorities can be changed in the rotating priority mode.
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For the master controller, ICW3 is used to indicate which IRQ input line is used to cascade the
slave controller. Within the ICH4, IRQ2 is used. Therefore, bit 2 of ICW3 on the master
controller is set to a 1, and the other bits are set to 0s.
For the slave controller, ICW3 is the slave identification code used during an interrupt
acknowledge cycle. On interrupt acknowledge cycles, the master controller broadcasts a code
to the slave controller if the cascaded interrupt won arbitration on the master controller. The
slave controller compares this identification code to the value stored in its ICW3, and if it
matches, the slave controller assumes responsibility for broadcasting the interrupt vector.
OCW1 masks and unmasks interrupt lines.
OCW2 controls the rotation of interrupt priorities when in rotating priority mode and controls
the EOI function.
OCW3 is sets up ISR/IRR reads, enables/disables the special mask mode (SMM) and enables/
disables polled interrupt mode.
Functional Description
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