FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 339

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.4
Intel
®
Table 9-3. Interrupt Controller I/O Address Map (PIC Registers)
82801DBM ICH4-M Datasheet
8259 Interrupt Controller (PIC) Registers
The interrupt controller registers are located at 20h and 21h for the master controller (IRQ0
at A0h and A1h for the slave controller (IRQ8
depending upon the data written to them. Below is a description of the different register
possibilities for each address.
4D0h
4D1h
Port
A0h
A1h
20h
21h
B4h, B8h, BCh
B5h, B9h, BDh
34h, 38h, 3Ch
35h, 39h, 3Dh
ACh, B0h,
ADh, B1h,
A4h, A8h,
A5h, A9h,
2Ch, 30h,
2Dh, 31h,
24h, 28h,
25h, 29h,
Aliases
—
—
Master PIC ICW1 Init. Cmd Word 1 Register
Master PIC OCW2 Op Ctrl Word 2 Register
Master PIC OCW3 Op Ctrl Word 3 Register
Master PIC ICW2 Init. Cmd Word 2 Register
Master PIC ICW3 Init. Cmd Word 3 Register
Master PIC ICW4 Init. Cmd Word 4 Register
Master PIC OCW1 Op Ctrl Word 1 Register
Slave PIC ICW1 Init. Cmd Word 1 Register
Slave PIC OCW2 Op Ctrl Word 2 Register
Slave PIC OCW3 Op Ctrl Word 3 Register
Slave PIC ICW2 Init. Cmd Word 2 Register
Slave PIC ICW3 Init. Cmd Word 3 Register
Slave PIC ICW4 Init. Cmd Word 4 Register
Slave PIC OCW1 Op Ctrl Word 1 Register
Master PIC Edge/Level Triggered Register
Slave PIC Edge/Level Triggered Register
Table 9-3
Register Name/Function
provides the register I/O map for the interrupt controller.
–
13). These registers have multiple functions,
LPC Interface Bridge Registers (D31:F0)
Default Value
001XXXXXb
001XXXXXb
X01XXX10b
X01XXX10b
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
01h
00h
01h
00h
00h
00h
Type
–
R/W
R/W
R/W
R/W
R/W
R/W
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
7), and
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