FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 161

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 5-45. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2)
82801DBM ICH4-M Datasheet
Addr
06h
07h
08h
20h
I/O
NOTES:
1. The OCW1 register must be read before entering ALT access mode.
2. Bits 5, 3, 1, and 0 return 0.
Rds
# of
12
2
2
6
Access
10
11
12
1
2
1
2
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9
Restore Data
DMA Chan 3 base address
low byte
DMA Chan 3 base address
high byte
DMA Chan 3 base count low
byte
DMA Chan 3 base count high
byte
DMA Chan 0–3 Command
DMA Chan 0–3 Request
DMA Chan 0 Mode: Bits(1:0)
= “00”
DMA Chan 1 Mode: Bits(1:0)
= “01”
DMA Chan 2 Mode: Bits(1:0)
= “10”
DMA Chan 3 Mode: Bits(1:0)
= “11”.
PIC ICW2 of Master controller
PIC ICW3 of Master controller
PIC ICW4 of Master controller
PIC OCW1 of Master
controller
PIC OCW2 of Master
controller
PIC OCW3 of Master
controller
PIC ICW2 of Slave controller
PIC ICW3 of Slave controller
PIC ICW4 of Slave controller
PIC OCW1 of Slave
controller
PIC OCW2 of Slave controller
PIC OCW3 of Slave controller
1
1
Data
2
Addr
CAh
CCh
CEh
C6h
C8h
D0h
I/O
Rds
# of
2
2
2
2
2
6
Access
1
2
1
2
1
2
1
2
1
2
1
2
3
4
5
6
Restore Data
DMA Chan 5 base count low
byte
DMA Chan 5 base count high
byte
DMA Chan 6 base address low
byte
DMA Chan 6 base address high
byte
DMA Chan 6 base count low
byte
DMA Chan 6 base count high
byte
DMA Chan 7 base address low
byte
DMA Chan 7 base address high
byte
DMA Chan 7 base count low
byte
DMA Chan 7 base count high
byte
DMA Chan 4–7 Command
DMA Chan 4–7 Request
DMA Chan 4 Mode: Bits(1:0) =
00
DMA Chan 5 Mode: Bits(1:0) =
01
DMA Chan 6 Mode: Bits(1:0) =
10
DMA Chan 7 Mode: Bits(1:0) =
11.
Functional Description
Data
2
161