FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 513

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

14.2.11
Intel
®
82801DBM ICH4-M Datasheet
SDM—SDATA_IN Map Register
I/O Address:
Default Value:
Lockable:
Reads across DWord boundaries are not supported.
Bit
7:6
5:4
1:0
3
2
PCM In 2, Microphone In 2 Data In Line (DI2L) — R/W. When the SE bit is set, these bits indicate
which AC_SDIN line should be used by the hardware for decoding the input slots for PCM In 2 and
Microphone In 2. When the SE bit is cleared, the value of these bits are irrelevant, and PCM In 2
and Mic In 2 DMA engines are not available.
00 = AC_SDIN0
01 = AC_SDIN1
10 = AC_SDIN2
11 = Reserved
PCM In 1, Microphone In 1 Data In Line (DI1L) — R/W. When the SE bit is set, these bits indicate
which AC_SDIN line should be used by the hardware for decoding the input slots for PCM In 1 and
Microphone In 1. When the SE bit is cleared, the value of these bits are irrelevant, and the PCM In 1
and Mic In 1 engines use the OR’d AC_SDIN lines.
00 = AC_SDIN0
01 = AC_SDIN1
10 = AC_SDIN2
11 = Reserved
Steer Enable (SE) — R/W. When set, the AC_SDIN lines are treated separately and not OR’d
together before being sent to the DMA engines. When cleared, the AC_SDIN lines are OR’d
together, and the “Microphone In 2” and “PCM In 2” DMA engines are not available.
Reserved — RO.
Last Codec Read Data Input (LDI) — RO. When a codec register is read, this indicates which
AC_SDIN the read data returned on. Software can use this to determine how the codecs are
mapped. The values are:
00 = AC_SDIN0
01 = AC_SDIN1
10 = AC_SDIN2
11 = Reserved
NABMBAR + 80h
00h
No
Description
AC ’97 Audio Controller Registers (D31:F5)
Attribute:
Size:
Power Well:
R/W, RO
8 bits
Core
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