FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 408

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

IDE Controller Registers (D31:F1)
10.1.18
10.1.19
10.1.20
408
INTR_LN—Interrupt Line Register (IDE—D31:F1)
Address Offset:
Default Value:
INTR_PN—Interrupt Pin Register (IDE—D31:F1)
Address Offset:
Default Value:
IDE_TIM — IDE Timing Register (IDE—D31:F1)
Address Offset:
Default Value:
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It
also controls operation of the buffer for PIO transfers.
13:12
Bit
7:0
7:3
2:0
15
14
Bit
Bit
IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or Secondary decode.
The IDE I/O Space Enable bit in the Command register must be set for this bit to have any effect.
Additionally, separate configuration bits are provided (in the IDE I/O Configuration register) to
individually disable the primary or secondary IDE interface signals, even if the IDE Decode Enable
bit is set.
0 = Disable.
1 = Enables the ICH4 to decode the associated Command Blocks (1F0–1F7h for primary,
This bit effects the IDE decode ranges for both legacy and native-Mode decoding. It also effects the
corresponding primary or secondary memory decode range for IDE Expansion.
Drive 1 Timing Register Enable (SITRE) — R/W.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1.
IORDY Sample Point (ISP) — R/W. The setting of these bits determine the number of PCI clocks
between IDE IOR#/IOW# assertion and the first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Interrupt Line (INT_LN) — R/W. It is to communicate to software the interrupt line that the
interrupt pin is connected to.
Reserved
Interrupt Pin (INT_PN) — RO. The value of 01h indicates to “software” that the ICH4 will drive
INTA#. Note that this is only used in native mode. Also note that the routing to the internal interrupt
controller does not necessarily relate to the value in this register. The IDE interrupt is in fact routed
to PIRQ[C]# (IRQ18 in APIC mode).
170–177h for secondary) and Control Block (3F6h for primary and 376h for secondary).
3Ch
3Dh
Primary:
00h
01h
Secondary: 42
0000h
40
–
–
41h
43h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Intel
RO
8 bits
R/W
16 bits
R/W
8 bits
®
82801DBM ICH4-M Datasheet