FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 157

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.12.10
5.12.10.1
Intel
®
Table 5-43. Transitions Due to Power Button
82801DBM ICH4-M Datasheet
Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The
becomes deasserted during these transitions. Normally, this would indicate to the system
electronics that a power-on reset be performed, which would invalidate the system context. ICH4
prevents this from occurring by maintaining CPUPWRGOOD during the transition.
CPUPWRGOOD must also be maintained during an S1-M state.
Event Input Signals and Their Usage
The ICH4 has various input signals that trigger specific events. This section describes those signals
and how they should be used.
PWRBTN# - Power Button
The ICH4 PWRBTN# signal operates as a “Fixed Power Button” as described in the ACPI
specification. PWRBTN# signal has a 16 ms de-bounce on the input. The state transition
descriptions are included in
pressed (but after the debounce logic), and does not depend on when the Power Button is released.
Power Button Override Function
If PWRBTN# is observed active for at least four consecutive seconds, then the state machine
should unconditionally transition to the G2/S5 state, regardless of present state (S0–S4). In this
case, the transition to the G2/S5 state should not depend on any particular response from the
processor (e.g., a Stop-Grant cycle), nor any similar dependency from any other subsystem.
New: A power button override will force a transition to S5, even if PWROK is not active
The PWRBTN# status is readable to check if the button is currently being pressed or has been
released. The status is taken after the de-bounce, and is readable via the PWRBTN_LVL bit.
4-second timer starts counting when the ICH4 is in a S0 state. If the PWRBTN# signal is asserted
and held active when the system is in a suspend state (S1-M–S5), the assertion causes a wake
event. Once the system has resumed to the S0 state, the 4-second timer starts.
S1-M–S5
Present
S0–S4
S0/Cx
State
G3
PWRBTN# held low for
at least 4 consecutive
PWRBTN# goes low
PWRBTN# goes low
PWRBTN# pressed
seconds
Event
Table
5-43. Note that the transitions start as soon as the PWRBTN# is
Wake Event. Transitions to
Unconditional transition to S5
(depending on SCI_EN)
SMI# or SCI generated
Transition/Action
S0 state.
None
state.
Software will typically initiate a
Sleep state.
Standard wakeup
No effect since no power.
Not latched nor detected.
No dependence on processor
(e.g., Stop-Grant cycles) or any
other subsystem.
Functional Description
Comment
.
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