FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 137

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.11.1.3
Intel
®
Table 5-30. INIT# Going Active
Figure 5-12. Coprocessor Error Timing Diagram
82801DBM ICH4-M Datasheet
FERR#/IGNNE# (Coprocessor Error)
The ICH4 supports the coprocessor error function with the FERR#/IGNNE# pins. The function is
enabled via the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0, bit 13). FERR# is tied
directly to the Coprocessor Error signal of the processor. If FERR# is driven active by the
processor, IRQ13 goes active (internally). When it detects a write to the COPROC_ERR register,
the ICH4 negates the internal IRQ13 and drives IGNNE# active. IGNNE# remains active until
FERR# is driven inactive. IGNNE# is never driven active unless FERR# is active.
If COPROC_ERR_EN is not set, then the assertion of FERR# will have not generate an internal
IRQ13, nor will the write to F0h generate IGNNE#.
Shutdown special cycle from processor.
PORT92 write, where INIT_NOW (bit 0) transitions
from a 0 to a 1.
PORTCF9 write, where SYS_RST (bit 1) was a 0 and
RST_CPU (bit 2) transitions from 0 to 1.
RCIN# input signal goes low. RCIN# is expected to be
driven by the external microcontroller (KBC).
CPU BIST
I/O Write to F0h
Cause of INIT# Going Active
Internal IRQ13
IGNNE#
FERR#
0 to 1 transition on RCIN# must occur before the
ICH4 will arm INIT# to be generated again.
NOTE: RCIN# signal is expected to be high during
To enter BIST, the software sets CPU_BIST_EN bit
and then does a full processor reset using the CF9
register.
S1-M and low during S3, S4, and S5 states.
Transition on the RCIN# signal in those
states (or the transition to those states) may
not necessarily cause the INIT# signal to be
generated to the processor.
Comment
Functional Description
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