FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 477

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

13.1.11
13.1.12
13.1.13
Intel
®
82801DBM ICH4-M Datasheet
INTR_LN—Interrupt Line Register (SMBUS—D31:F3)
Address Offset:
Default Value:
INTR_PN—Interrupt Pin Register (SMBUS—D31:F3)
Address Offset:
Default Value:
HOSTC—Host Configuration Register (SMBUS—D31:F3)
Address Offset:
Default Value:
7:0
Bit
7:0
Bit
7:3
Bit
2
1
0
Interrupt Line (INT_LN) — R/W. This data is not used by the ICH4. It is to communicate to software
the interrupt line that the interrupt pin is connected to PIRQB#.
Reserved
I
0 = SMBus behavior.
1 = The ICH4 is enabled to communicate with I
SMB_SMI_EN — R/W. This bit needs to be set for SMBALERT# to be enabled.
0 = SMBus interrupts will not generate an SMI#.
1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer to
SMBus Host Enable ( HST_EN) — R/W.
0 = Disable the SMBus Host Controller.
1 = Enable. The SMB Host Controller interface is enabled to execute commands. The INTREN bit
Interrupt Pin (INT_PN) — RO.
02h = Indicates that the ICH4 SMBus Controller will drive PIRQB# as its interrupt line.
2
C_EN — R/W.
commands.
Section 5.18.4
needs to be enabled for the SMB Host Controller to interrupt or SMI#. Note that the SMB Host
Controller will not respond to any new requests until all interrupt requests have been cleared.
3Ch
00h
3Dh
02h
40h
00h
(Interrupts / SMI#).
Description
Description
Description
Attributes:
Size:
Attributes:
Size:
Attribute:
Size:
2
C devices. This will change the formatting of some
SMBus Controller Registers (D31:F3)
R/W
8 bits
RO
8 bits
R/W
8 bits
477