FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 267

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

7.1.3
Intel
®
82801DBM ICH4-M Datasheet
PCICMD—PCI Command Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved
Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The integrated LAN* Controller will not run
fast back-to-back PCI cycles.
SERR# Enable (SERR_EN) — R/W.
0 = Disable.
1 = Enable. Allow SERR# to be asserted.
Wait Cycle Control (WCC) — RO. Hardwired to 0. Not implemented.
Parity Error Response (PER) — R/W
0 = The LAN Controller will ignore PCI parity errors.
1 = The integrated LAN Controller will take normal action when a PCI parity error is detected and
VGA Palette Snoop (VPS) — RO. Hardwired to 0. Not Implemented.
Memory Write and Invalidate Enable (MWIE) — R/W.
0 = Disable. The LAN* Controller will not use the Memory Write and Invalidate command.
1 = Enable.
Special Cycle Enable (SCE) — RO. Hardwired to 0. The LAN Controller ignores special cycles.
Bus Master Enable (BME) — R/W.
0 = Disable.
1 = Enable. The ICH4’s integrated may function as a PCI bus master.
Memory Space Enable (MSE) — R/W.
0 = Disable.
1 = Enable. The ICH4’s integrated LAN Controller will respond to the memory space accesses.
I/O Space Enable (IOSE) — R/W.
0 = Disable.
1 = Enable. The ICH4’s integrated LAN Controller will respond to the I/O space accesses.
will enable generation of parity on the hub interface.
04
0000h
–
05h
Description
Attribute:
Size:
LAN Controller Registers (B1:D8:F0)
R/W, RO
16 bits
267