FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 486

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

SMBus Controller Registers (D31:F3)
13.2.16
13.2.17
486
Note: This register is in the resume well and is reset by RSMRST#
Note: This register is in the resume well and is reset by RSMRST#
SLV_CMD—Slave Command Register
Register Offset:
Default Value:
NOTIFY_DADDR—Notify Device Address
Register Offset:
Default Value:
7:2
7:1
Bit
Bit
2
1
0
0
Reserved
SMBALERT_DIS — R/W.
0 = Allows the generation of the interrupt or SMI#.
1 = Software sets this bit to block the generation of the interrupt or SMI# due to the SMBALERT#
HOST_NOTIFY_WKEN — R/W.
0 = Disable.
1 = Enables the reception of a Host Notify command as a wake event. When enabled this event is
HOST_NOTIFY_INTREN — R/W.
0 = Disable
1 = Enables the generation of interrupt or SMI# when HOST_NOTIFY_STS is 1. This enable does
DEVICE_ADDRESS — RO. This field contains the 7-bit device address received during the Host
Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when the
HOST_NOTIFY_STS bit is set to 1.
Reserved
source. This bit is logically inverted and ANDed with the SMBALERT_STS bit. The resulting
signal is distributed to the SMI# and/or interrupt generation logic. This bit does not effect the
wake logic.
“OR”ed in with the other SMBus wake events and is reflected in the SMB_WAK_STS bit of the
General Purpose Event 0 Status register.
not affect the setting of the HOST_NOTIFY_STS bit. When the interrupt is generated, either
PIRQ[B]# or SMI# is generated, depending on the value of the SMB_SMI_EN bit (D31, F3,
Off40h, B1). If the HOST_NOTIFY_STS bit is set when this bit is written to a 1, then the interrupt
(or SMI#) will be generated. The interrupt (or SMI#) is logically generated by AND’ing the STS
and INTREN bits.
11h
14h
00h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/W
8 bits
RO
8 bits