FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 465

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

12.2.2.9
Intel
®
82801DBM ICH4-M Datasheet
PORTSC—Port N Status and Control Register
Offset:
Attribute:
Default Value:
A host controller must implement one or more port registers. Software uses the N_Port information
from the Structural Parameters Register to determine how many ports need to be serviced. All ports
have the structure defined below. Software must not write to unreported Port Status and Control
Registers.
This register is in the suspend power well. It is only reset by hardware when the suspend power is
initially applied or in response to a host controller reset. The initial conditions of a port are:
When a device is attached, the port state transitions to the attached state and system software will
process this as with any status change notification. Refer to Chapter 4 of the Enhanced Host
Controller Interface (EHCI) Specification for Universal Serial Bus for operational requirements
for how change events interact with port suspend mode.
•
•
31:23
19:16
Bit
22
21
20
No device connected,
Port disabled.
Reserved. These bits are reserved for future use and will return a value of 0s when read.
Wake on Over-current Enable (WKOC_E) — RW.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Wake on Disconnect Enable (WKDSCNNT_E) — RW. Default = 0b.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Wake on Connect Enable (WKCNNT_E) — RW.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Port Test Control — RW. When this field is 0, the port is NOT operating in a test mode. A non-zero
value indicates that it is operating in test mode and the specific test mode is indicated by the specific
value. Refer to Universal Serial Bus (USB) Specification, Revision 2.0 , Chapter 7 for details on each
test mode.
BitsTest Mode
0000Test mode Not enabled (Default)
0001Test J_STATE
0010Test K_STATE
0011Test SE0_NAK
0100Test Packet
0101Test FORCE_ENABLE
0110–1111Reserved
Management Control/Status Register (offset 54, bit 15) when the Over-current Active bit (bit 4
of this register) is set to 1.
Management Control/Status Register (offset 54, bit 15) when the Current Connect Status
changes from connected to disconnected (i.e., bit 0 of this register changes from 1 to 0).
Management Control/Status Register (offset 54, bit 15) when the Current Connect Status
changes from disconnected to connected (i.e., bit 0 of this register changes from 0 to 1).
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
R/W, R/WC, RO
00003000h
CAPLENGTH + 44
CAPLENGTH + 48
CAPLENGTH + 4C
CAPLENGTH + 50
CAPLENGTH + 54
CAPLENGTH + 58
–
–
–
–
–
–
47h
4Bh
53h
57h
5Bh
Description
4Fh
Size:
EHCI Controller Registers (D29:F7)
32 bits
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