FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 268

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LAN Controller Registers (B1:D8:F0)
7.1.4
268
PCISTS—PCI Status Register (LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
10:9
Bit
3:0
15
14
13
12
11
8
7
6
5
4
Detected Parity Error (DPE) — R/WC.
0 = This bit is cleared by writing a 1 to the bit location.
1 = The ICH4’s integrated LAN* Controller has detected a parity error on the PCI bus (will be set
Signaled System Error (SSE)
0 = This bit is cleared by writing a 1 to the bit location.
1 = The ICH4’s integrated LAN Controller has asserted SERR#. (SERR# can be routed to cause
Master Abort Status (MAS) — R/WC.
0 = This bit is cleared by writing a 1 to the bit location.
1 = The ICH4’s integrated LAN Controller (as a PCI master) has generated a master abort.
Received Target Abort (RTA) — R/WC.
0 = This bit is cleared by writing a 1 to the bit location.
1 = The ICH4’s integrated LAN Controller (as a PCI master) has received a target abort.
Signaled Target Abort (STA) — RO. Hardwired to 0. The device will never signal Target Abort.
DEVSEL# Timing Status (DEV_STS) —RO.
01h = Medium timing.
Data Parity Error Detected (DPED) — R/WC.
0 = This bit is cleared by writing a 1 to the bit location.
1 = All of the following three conditions have been met:
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. The device can accept fast back-to-
back transactions.
User Definable Features (UDF) — RO. Hardwired to 0. Not implemented.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. The device does not support 66 MHz PCI.
Capabilities List (CAP_LIST) — RO.
0 = The EEPROM indicates that the integrated LAN controller does not support PCI Power
1 = The EEPROM indicates that the integrated LAN controller supports PCI Power Management.
Reserved
1. The LAN Controller is acting as bus master
2. The LAN Controller has asserted PERR# (for reads) or detected PERR# asserted (for writes)
3. The Parity Error Response bit in the LAN Controller’s PCI Command Register is set.
even if Parity Error Response is disabled in the PCI Command register).
NMI, SMI# or interrupt.
Management.
06
0290h
–
07h
—
R/WC.
Description
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/WC, RO
16 bits