FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 317

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801DBM ICH4-M Datasheet
Bit
5:4
8
7
6
3
2
1
0
APIC Enable (APIC_EN) — R/W.
0 = Disables internal I/O (x) APIC.
1 = Enables the internal I/O (x) APIC and its address decode.
The following behavioral rules apply for bits 8 and 7 in this register:
NOTE: There is no separate way to disable PCI Message Interrupts if the I/O (x) APIC is enabled.
I/O (x) Extension Enable (XAPIC_EN) — R/W.
0 = The I/O (x) APIC extensions are not supported.
1 = Enables the extra features (beyond standard I/O APIC) associated with the I/O (x) APIC.
NOTE: This bit is only valid if the APIC_EN bit is also set to 1.
Alternate Access Mode Enable (ALTACC_EN) — R/W.
0 = Alt Access Mode Disabled (default). ALT access mode allows reads to otherwise unreadable
1 = Alt Access Mode Enable.
Reserved
: Mobile IDE Configuration Lock Down (MICLD) — R/WO.
0 = No lock
1 = When set, Bits 7:6 of the Backed up Control Register (Offset D5h)can no longer be written until
DMA Collection Buffer Enable (DCB_EN) — R/W.
0 = DCB disabled.
1 = Enables DMA Collection Buffer (DCB) for LPC I/F and PC/PCI DMA.
Delayed Transaction Enable (DTE) — R/W.
0 = Delayed transactions disabled.
1 = ICH4 enables delayed transactions for internal register, FWH and LPC I/F accesses.
Positive Decode Enable (POS_DEC_EN) — R/W.
0 = The ICH4 will perform subtractive decode on the PCI bus and forward the cycles to LPC I/F if
1 = Enables ICH4 to only perform positive decode on the PCI bus.
• Rule 1: If bit 8 is 0, the ICH4 does not decode any of the registers associated with the I/O APIC
• Rule 2: If bit 8 is 1 and bit 7 is 0, the ICH4 decodes the memory space associated with the I/O
• Rule 3: If bit 8 is 1 and bit 7 is 1, the ICH4 decodes the memory space associated with both the
or I/O (x) APIC. The state of bit 7 is “Don’t Care” in this case.
APIC, but not the extra registers associated I/O (x) APIC.
I/O APIC and the I/O (x) APIC. This also enables PCI masters to write directly to the register to
cause interrupts (PCI Message Interrupt).
registers and writes otherwise unwritable registers.
a PCI reset occurs. This prevents rogue software from changing the default state of the IDE
pins during boot after BIOS configures them. This bit is write once, and is cleared by PCIRST#
and when returning from the S3/S4/S5 states.
not to an internal register or other known target on the LPC I/F. Accesses to internal registers
and to known LPC I/F devices will still be positively decoded.
This is not considered necessary.
Description
LPC Interface Bridge Registers (D31:F0)
317