FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 214

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.17.6
5.17.6.1
5.17.7
5.17.7.1
214
USB EHCI Interrupts and Error Conditions
Section 4 of the EHCI specification goes into detail on the EHC interrupts and the error conditions
that cause them. All error conditions that the EHC detects can be reported through the EHCI
Interrupt status bits. Only ICH4-specific interrupt and error-reporting behavior is documented in
this section. The EHCI Interrupts Section must be read first, followed by this section of the
datasheet to fully comprehend the EHC interrupt and error-reporting functionality.
Aborts on USB EHCI-Initiated Memory Reads
If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The following
actions are taken when this occurs:
USB EHCI Power Management
Pause Feature
This feature allows platforms (especially mobile systems) to dynamically enter low-power states
during brief periods when the system is idle (i.e., between keystrokes). This is useful for enabling
power management features like C3, C4, and Intel SpeedStep technology in the ICH4. The policies
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Based on the EHC’s buffer sizes and buffer management policies, the Data Buffer Error can
never occur on the ICH4.
Master Abort and Target Abort responses from hub interface on EHC-initiated read packets
will be treated as Fatal Host Errors. The EHC halts when these conditions are encountered.
The ICH4 may assert the interrupts which are based on the interrupt threshold as soon as the
status for the last complete transaction in the interrupt interval has been posted in the internal
write buffers. The requirement in the EHCI Specification (that the status is written to memory)
is met internally, even though the write may not be seen on the hub interface before the
interrupt is asserted.
Since the ICH4 supports the 1024-element Frame List size, the Frame List Rollover interrupt
occurs every 1024 milliseconds.
The ICH4 delivers interrupts using PIRQ#[H].
The ICH4 does not modify the CERR count on an Interrupt IN when the “Do Complete-Split”
execution criteria are not met.
For complete-split transactions in the Periodic list, the “Missed Microframe” bit does not get
set on a control-structure-fetch that fails the late-start test. If subsequent accesses to that
control structure do not fail the late-start test, then the “Missed Microframe” bit will get set
and written back.
The Host System Error status bit is set
The DMA engines are halted after completing up to one more transaction on the USB interface
If enabled (by the Host System Error Enable), an interrupt is generated
If the status is Master Abort, the Received Master Abort bit in configuration space is set
If the status is Target Abort, the Received Target Abort bit in configuration space is set
If enabled (by the SERR Enable bit in the function’s configuration space), the Signaled System
Error bit in configuration bit is set.
Intel
®
82801DBM ICH4-M Datasheet