FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 395

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.9.10
9.9.11
Intel
®
82801DBM ICH4-M Datasheet
TCO_WDSTATUS—TCO2 Control Register
Offset Address:
Default Value:
Power Well:
SW_IRQ_GEN—Software IRQ Generation Register
Offset Address:
Default Value:
Power Well:
7:0
7:2
Bit
Bit
1
0
Watchdog Status (WDSTATUS) — R/W. The value written to this register will be sent in the Alert
On LAN message on the SMLINK interface. It can be used by the BIOS or system management
software to indicate more details on the boot progress. This register will be reset to the default of
00h based on RSMRST# (but not PCI reset).
Reserved
IRQ12_CAUSE
by the ICH4’s SERIRQ logic. This bit must be a 1 (default) if the ICH4 is expected to receive IRQ12
assertions from a SERIRQ device.
IRQ1_CAUSE
the ICH4’s SERIRQ logic. This bit must be a 1 (default) if the ICH4 is expected to receive IRQ1
assertions from a SERIRQ device.
TCOBASE + 0Eh
00h
Resume
TCOBASE + 10h
11h
Core
—
—
R/W. The state of this bit is logically ANDed with the IRQ1 signal as received by
R/W. The state of this bit is logically ANDed with the IRQ12 signal as received
Description
Description
Attribute:
Size:
Attribute:
Size:
LPC Interface Bridge Registers (D31:F0)
R/W
8 bits
R/W
8 bits
395