FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 176

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
176
Table 5-51. IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select)
Table 5-52. IDE Legacy I/O Ports: Control Block Registers (CS3x# Chip Select)
Note: The Data Register (I/O Offset 00h) should be accessed using 16-bit or 32-bit I/O instructions. All
The IDE I/O ports involved in PIO transfers are decoded by the ICH4 to the IDE interface when
D31:F1 I/O space is enabled and IDE decode is enabled through the IDE_TIMx registers. The IDE
registers are implemented in the drive itself. An access to the IDE registers results in the assertion
of the appropriate IDE chip select for the register, and the IDE command strobes (PDIOR#/
SDIOR#, PDIOW#/SDIOW#).
There are two I/O ranges for each IDE cable: the Command Block, which corresponds to the
PCS1#/SCS1# chip select, and the Control Block, which corresponds to the PCS3#/SCS3# chip
select. The Command Block is an 8-byte range, while the control block is a 4-byte range.
Table 5-51
other registers should be accessed using 8-bit I/O instructions.
NOTE: For accesses to the Alt Status register in the Control Block, the ICH4 must always force the upper
In native mode, the ICH4 does not decode the legacy ranges. The same offsets are used as in
Table 5-51
rather than fixed I/O locations.
I/O Offset
I/O Offset
— Command Block Offset: 01F0h for primary, 0170h for secondary
— Control Block Offset: 03F4h for primary, 0374h for secondary
00h
01h
02h
03h
04h
05h
06h
07h
00h
01h
02h
03h
address bit (PDA[2] or SDA[2]) to 1 in order to guarantee proper native mode decode by the IDE device.
Unlike the legacy mode fixed address location, the native mode address for this register may contain a 0
in address bit 2 when it is received by the ICH4.
and
and
Table 5-52
Table 5-52
Data
Error
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive
Status
Reserved
Reserved
Alt Status
Forward to LPC - Not Claimed by IDE
Register Function (Read)
Register Function (Read)
specify the registers as they affect the ICH4 hardware definition.
above. However, the base addresses are selected using the PCI BARs,
Data
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Head
Command
Reserved
Reserved
Device Control
Forward to LPC - Not Claimed by IDE
Intel
Register Function (Write)
Register Function (Write)
®
82801DBM ICH4-M Datasheet