FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 152

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
152
Table 5-40. Causes of Wake Events
Table 5-41. GPI Wake Events
NOTES:
It is important to understand that the various GPIs have different levels of functionality when used
as wake events. The GPIs that reside in the core power well can only generate wake events from an
S1-M state. Also only certain GPIs are “ACPI Compliant,” meaning that their Status and Enable
bits reside in ACPI I/O space.
The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply
design, so much so that the exit latencies due to the ICH4 are insignificant.
1. This will be a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP
2. If in the S5 state due to a powerbutton override, the possible wake events are due to Power Button, Hard
3. The entry for USB changes from being able to wake from S1-M
RTC Alarm
Power Button
GPI[0:n]
USB
LAN
RI#
AC ’97
Primary PME#
Secondary PME#
GST Timeout
SMBALERT#
SMBus Slave
Message
SMBus Host Notify
message received
PME_B0 (internal USB
EHCI controller)
bits via software.
Reset Without Cycling (See Command Type 3 in
Type 4 in
Previous designs actively blocked wake events while in S5. There is no need to do this as software already
disables waking from USB on S5 (so the wake bits are masked), and in the future power buttons will move to
USB keyboards, and a wake from S5 will be necessary.
GPI[13:11], GPI[8]
GPI[7:0]
Cause
GPI
Table
5-95).
States Can Wake
S1-M
S1-M
S1-M
S1-M
S1-M
S1-M
S1-M
S1-M
S1-M
S1-M
S1-M–S5
S1-M
S1-M
From
S1-M
Power Well
Table 5-41
–
–
–
–
–
–
Resume
S5
–
S5
S5
–
S5
–
–
S5
–
–
S5
Core
S5
S5
S5
S5
S5
S5
(1)
(1)
(3)
(1)
(1)
(1)
Set RTC_EN bit in PM1_EN register
Always enabled as Wake event
GPE0_EN register
Set USB1_EN, USB 2_EN and USB3_EN bits in GPE0_EN
register
Will use PME#. Wake enable set with LAN logic.
Set RI_EN bit in GPE0_EN register
Set AC ’97_EN bit in GPE0_EN register
PME_B0_EN bit in GPE0_EN register
Set PME_EN bit in GPE0_EN Register.
Setting the GST Timeout range to a value other than 00h.
Always enabled as Wake event
Wake/SMI# command always enabled as a Wake Event.
NOTE: SMBus Slave Message can wake the system from
HOST_NOTIFY_WKEN bit SMBus Slave Command register.
Reported in the SMB_WAK_STS bit in the GPEO_STS register.
Set PME_B0_EN bit in GPE0_EN register.
summarizes the use of GPIs as wake events.
Table
S1-M–S5, as well as from S5 due to Power Button
Override.
5-95), and Hard Reset System (See Command
Wake From
S1-M–S5
S1-M
–
S4 to being able to wake from S1-M
Intel
How Enabled
®
82801DBM ICH4-M Datasheet
ACPI Compliant
Notes
–
S5.