FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 460

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
460
Bit
3
2
1
0
Frame List Rollover — R/WC.
0 = No rollover.
1 = Frame List Rollover. The Host Controller sets this bit to a 1 when the Frame List Index (see
Port Change Detect — R/WC.
0 = Not Detected.
1 = Port Change Detected. The Host Controller sets this bit to a 1 when any port for which the Port
USB Error Interrupt (USBERRINT) — R/WC.
0 = No Error.
1 = Error Condition. The Host Controller sets this bit to 1 when completion of a USB transaction
USB Interrupt (USBINT) — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = The Host Controller sets this bit to 1 when one of the following occurs:
•The cause of an interrupt is a completion of a USB transaction whose Transfer Descriptor had
•The Host Controller also sets this bit to 1 when a short packet is detected (actual number of
Section) rolls over from its maximum value to zero. Since the ICH4 only supports the 1024-
entry Frame List Size, the Frame List Index rolls over every time FRNUM[13] toggles.
Owner bit is set to 0 has a change bit transition from 0 to 1 or a Force Port Resume bit transition
from 0 to 1 as a result of a J-K transition detected on a suspended port.
results in an error condition (e.g., error counter underflow). If the TD on which the error interrupt
occurred also had its IOC bit set, both this bit and Bit 0 are set. See the EHCI specification for a
list of the USB errors that will result in this interrupt being asserted.
its IOC bit set.
bytes received was less than the expected number of bytes).
Description
Intel
®
82801DBM ICH4-M Datasheet