FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 148

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.12.6
5.12.6.1
5.12.6.2
148
Note: The 33-MHz clock to the ICH4 is “free-running” and is not affected by the STP_PCI# signal.
Dynamic PCI Clock Control
The PCI clock can be dynamically controlled independent of any other low-power state. This
control is accomplished using the CLKRUN# protocol as described in the PCI Mobile Design
Guide, and is transparent to software.
The Dynamic PCI Clock control is handled using the following signals:
Conditions for Stopping the PCI Clock
When there is a lack of PCI activity, the ICH4 has the capability to stop the PCI clocks to conserve
power. “PCI activity” is defined as any activity that would require the PCI clock to be running.
Any of the following conditions will indicate that it is NOT OK to stop the PCI clock:
Behavioral Description
Conditions for Maintaining the PCI Clock
PCI masters or LPC devices that wish to maintain the PCI clock running will observe the
CLKRUN# signal deasserted, and then must re-assert if (drive it low) within 3 clocks.
Behavioral Description
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CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run
STP_PCI#: Used to stop the system PCI clock
Cycles on PCI or LPC
Cycles of any internal device that would need to go on the PCI bus
Cycles using PC/PCI DMA
SERIRQ activity
When there is a lack of activity (as defined above) for 29 PCI clocks, the ICH4 deassert (drive
high) CLKRUN# for 1 clock and then tri-state the signal.
When the ICH4 has tri-stated the CLKRUN# signal after deasserting it, the ICH4 then checks
to see if the signal has been re-asserted (externally).
After observing the CLKRUN# signal asserted for 1 clock, the ICH4 again starts asserting the
signal.
If an internal device needs the PCI bus, the ICH4 asserts the CLKRUN# signal.
Intel
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82801DBM ICH4-M Datasheet