FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 491

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

14.1.3
Intel
®
82801DBM ICH4-M Datasheet
PCICMD—PCI Command Register (Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
PCICMD is a 16-bit control register. Refer to the PCI 2.2 specification for complete details on each
bit.
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved. Read 0.
Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.
SERR# Enable (SERR_EN) — RO. Not implemented. Hardwired to 0.
Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.
Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.
VGA Palette Snoop (VPS) — RO. Not implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Not implemented. Hardwired to 0.
Bus Master Enable (BME) — R/W. This bit controls standard PCI bus mastering capabilities.
0 = Disable (Default).
1 = Enable
Memory Space Enable (MSE) — R/W. This bit enables memory space addresses to the AC ’97
Audio Controller. (Default=0).
0 = Disable (Default)
1 = Enable
I/O Space Enable (IOSE) — R/W. This bit controls access to the AC ’97 Audio Controller I/O
space registers.
0 = Disable (Default)
1 = Enable access to I/O space. The Native PCI Mode Base Address register should be
NOTE: This bit becomes write-able when the IOSE bit in offset 41h is set. If at any point software
programmed prior to setting this bit.
decides to clear the IOSE bit, software must first clear the IOS bit first.
04
0000h
No
–
05h
Description
AC ’97 Audio Controller Registers (D31:F5)
Attribute:
Size:
Power Well:
R/W, RO
16 bits
Core
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