FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 264

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Register and Memory Mapping
6.4.1
264
Table 6-4. Memory Decode Ranges from Processor Perspective (Sheet 2 of 2)
Note: The top-block swap mode may be forced by an external strapping option (See
Note: Top-block swap mode only affects accesses to the FWH BIOS space, not feature space.
Note: The top-block swap mode has no effect on accesses below FFFE_0000.
NOTES:
Boot-Block Update Scheme
The ICH4 supports a “top-block swap” mode that has the ICH4 swap the top block in the FWH (the
boot block) with another location. This allows for safe update of the Boot Block (even if a power
failure occurs). When the “TOP_SWAP” Enable bit is set, the ICH4 will invert A16 for cycles
targeting FWH BIOS space. When this bit is 0, the ICH4 will not invert A16. This bit is
automatically set to 0 by RTCRST#, but not by PCIRST#.
The scheme is based on the concept that the top block is reserved as the “boot” block, and the block
immediately below the top block is reserved for doing boot-block updates.
The algorithm is:
If a power failure occurs at any point after step 3, the system will be able to boot from the copy of
the boot block that is stored in the block below the top. This is because the TOP_SWAP bit is
backed in the RTC well.
When top-block swap mode is forced in this manner, the TOP_SWAP bit cannot be cleared by
software. A re-boot with the strap removed will be required to exit a forced top-block swap mode.
1. These ranges are decoded directly from the hub interface. The memory cycles will not be seen on PCI.
2. Software must not attempt locks to memory mapped I/O ranges for USB EHCI and IDE Expansion. If
1. Software copies the top block to the block immediately below the top
2. Software checks that the copied block is correct. This could be done by performing a
3. Software sets the TOP_SWAP bit. This will invert A16 for cycles going to the FWH. CPU
4. Software erases the top block
5. Software writes the new top block
6. Software checks the new top block
7. Software clears the TOP_SWAP bit
attempted, the lock is not honored, which means potential deadlock conditions may occur.
1 kB anywhere in 4 GB
1 kB anywhere in 4 GB
checksum calculation.
access to FFFF_0000 through FFFF_FFFF will be directed to FFFE_0000 through
FFFE_FFFF in the FWH, and processor accesses to FFFE_0000 through FFFE_FFFF will be
directed to FFFF_0000 through FFFF_FFFF.
Memory Range
All other
range
range
IDE Expansion
Controller
USB EHCI
Target
PCI
1,2
2
Enable via standard PCI mechanism and bits in IDE I/O
Configuration Register (Device 31, Function 1)
Enable via standard PCI mechanism (Device 29, Function
7)
None
Dependency/Comments
Intel
®
82801DBM ICH4-M Datasheet
Section
2.20.1).