FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 401

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

10
10.1
Intel
®
Table 10-1. PCI Configuration Register Address Map (IDE—D31:F1)
82801DBM ICH4-M Datasheet
Note: Registers that are not shown should be treated as Reserved (See
PCI Configuration Registers (IDE—D31:F1)
All of the IDE registers are in the core well. None can be locked.
NOTES:
IDE Controller Registers (D31:F1)
1. The ICH4 IDE controller is not arbitrated as a PCI device, therefore it does not need a master latency timer.
2. Refer to the ICH4 Specification Update for the value of the Revision ID Register.
2C–2Dh
1C–1Fh
2E–2Fh
4A–4Bh
00–01h
02–03h
04–05h
06–07h
10–13h
14–17h
18–1Bh
20–23h
24–27h
40–41h
42–43h
Offset
0Ah
0Bh
0Dh
0Eh
08h
09h
44h
48h
54h
3C
3D
IDE_CONFIG
PCMD_BAR
SCMD_BAR
PCNL_BAR
SCNL_BAR
Mnemonic
IDE_TIMP
SDMATIM
INTR_PN
INTR_LN
ID_TIMS
SIDETIM
SDMAC
EXBAR
HTYPE
CMD
SVID
SCC
BCC
STS
BAR
MLT
VID
DID
RID
SID
PI
Vendor ID
Device ID
Command Register
Device Status
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Master Latency Timer (Note 1)
Header Type
Primary Command Block Base Address
Primary Control Block Base Address
Secondary Command Block Base
Address
Secondary Control Block Base Address
Base Address Register
Expansion BAR
Subsystem Vendor ID
Subsystem ID
Interrupt Line
Interrupt Pin
Primary IDE Timing
Secondary IDE Timing
Slave IDE Timing
Synchronous DMA Control Register
Synchronous DMA Timing Register
IDE I/O Configuration Register
Register Name
IDE Controller Registers (D31:F1)
Section 6.2
See Note 2
00000001h
00000001h
00000001h
00000001h
00000001h
Default
24CAh
8086h
0280h
0000h
0000h
0000h
8Ah
00h
01h
01h
00h
00h
00h
00h
00h
00
00
00
00
01
for details).
R/WC, RO
R/W, RO
R/WO
R/WO
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
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