NQ5000P S L9TN

Manufacturer Part NumberNQ5000P S L9TN
ManufacturerIntel
NQ5000P S L9TN datasheet
 


Specifications of NQ5000P S L9TN

MountingSurface MountLead Free Status / RoHS StatusNot Compliant
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Intel
5000P/5000V/5000Z Chipset
Memory Controller Hub (MCH)
Datasheet
September 2006
Document Number: 313071-003

NQ5000P S L9TN Summary of contents

  • Page 1

    ... Intel 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet September 2006 Document Number: 313071-003 ...

  • Page 2

    ... BIOS. Performance will vary depending on your hardware and software configurations. Intel EM64T-enabled OS, BIOS, device drivers and applications may not be available. Check with your vendor for more information.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ...

  • Page 3

    ... Reset Requirements........................................................................................... 38 2.10.1 Timing Diagrams .................................................................................... 38 2.10.2 Reset Timing Requirements ..................................................................... 40 2.10.3 Miscellaneous Requirements and Limitations .............................................. 41 2.11 Intel 5000P Chipset Platform Signal Routing Topology Diagrams .............................. 42 2.11.1 Intel 5000P Customer Reference Platform (SRP) Reset Topology................... 43 2.12 Signals Used as Straps....................................................................................... 43 2.12.1 Functional Straps ................................................................................... 43 3 Register Description.................................................................................................... 45 3 ...

  • Page 4

    ... Message Signalled Interrupt Next Pointer Register ................... 259 3.10.11MSICTRL - Message Signalled Interrupt Control Register ............................ 259 3.10.12MSIAR: Message Signalled Interrupt Address Register ............................... 261 3.10.13MSIDR: Message Signalled Interrupt Data Register.................................... 261 3.10.14PEXCAPID: PCI Express Capability ID Register .......................................... 262 4 Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet ...

  • Page 5

    ... FSB Overview ...................................................................................... 297 5.1.2 FSB Dynamic Bus Inversion ................................................................... 297 5.1.3 FSB Interrupt Overview......................................................................... 298 5.2 System Memory Controller ............................................................................... 298 5.2.1 Memory Population Rules ...................................................................... 300 5.2.2 Fully Buffered DIMM Technology and Organization .................................... 303 Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet 5 ...

  • Page 6

    ... End-of-Interrupt (EOI) Support .............................................................. 342 5.11.6 Error Handling...................................................................................... 342 5.12 PCI Express Ports ............................................................................................ 342 5.12.1 Intel 5000P Chipset MCH PCI Express Port Overview ................................. 343 5.12.2 Enterprise South Bridge Interface (ESI) ................................................... 344 5.12.3 PCI Express Ports 2 and 3 ...................................................................... 344 5.12.4 PCI Express General Purpose Ports.......................................................... 345 5 ...

  • Page 7

    ... Boundary Scan Register ........................................................................ 413 8.2 Extended Debug Port (XDP) .............................................................................. 414 9 Intel® 5000Z Chipset Differences ............................................................................... 415 9.1 Intel 5000Z Chipset Overview ........................................................................... 415 9.2 Fully Buffered DIMM (FB-DIMM) Memory ............................................................ 418 9.3 ESI Port ......................................................................................................... 418 Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet 7 ...

  • Page 8

    ... MCH to Intel 631xESB/632xESB I/O Controller Hub Enterprise South Bridge Interface ...................................................................... 340 5-16 x4 PCI Express Bit Lane.................................................................................... 343 5-17 ESI and PCI Express Ports 2 and 3 ..................................................................... 344 5-18 MCH to Intel 631xESB/632xESB I/O Controller Hub Port Configurations .................. 345 8 Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet ...

  • Page 9

    ... Intel 5000P Chipset MCH Ballout Right Side (Top View) ........................................ 443 10-5 Intel 5000V Chipset Quadrant Map .................................................................... 444 10-6 Intel 5000V Chipset MCH Ballout Left Side (Top View) .......................................... 445 10-7 Intel 5000V Chipset MCH Ballout Center (Top View) ............................................. 446 10-8 Intel 5000V Chipset MCH Ballout Right Side (Top View) ........................................ 447 10-9 Bottom View ...

  • Page 10

    ... Address Mapping Registers .................................................................................83 3-30 Register Offsets in AMB Memory Mapped Registers Region ......................................94 3-31 XTPR Index ..................................................................................................... 101 3-32 When Will a Intel 5000P Chipset PCI Express Device be Accessible?........................ 102 3-33 Intel 5000P Chipset MCH PCISTS and SECSTS Master/Data Parity Error RAS Handling ................................................................................. 114 3-1 GIO Port Mode Selection ...

  • Page 11

    ... MC.GTW_Mode=0 (normal) ........................................ 325 5-11 Electrical Throttle Window as a Function of DIMM Technology ................................ 326 5-12 XAPIC Data Encoding ....................................................................................... 328 5-13 Intel 5000P Chipset XAPIC Interrupt Message Routing and Delivery ....................... 329 5-14 Chipset Generated Interrupts............................................................................ 337 5-1 PCI Express Link Width Strapping Options for Port CPCI Configuration in MCH ...

  • Page 12

    ... Status Field Encoding for SMBus Reads............................................................... 368 5-24 MCH Supported SPD Protocols ........................................................................... 372 5-25 I/O Port Registers in I/O Extender supported by Intel 5000P Chipset MCH ............... 376 5-26 Hot-Plug Signals on a Virtual Pin Port ................................................................. 377 5-27 Intel 5000P Chipset MCH Frequencies for Processors and Core ............................... 378 5-28 Intel 5000P Chipset MCH Frequencies for Memory ...

  • Page 13

    ... Revision History Revision Number 001 Initial document release 002 Added support for Dual-Core Intel® Xeon® 5100 series 003 DMA section updated Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Description August 2006 § Date May 2006 June 2006 13 ...

  • Page 14

    ... Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet ...

  • Page 15

    ... The Intel 5000P chipset is designed for systems based on the Dual-Core Intel 5000 sequence and supports a FSB frequency up to 1333 MTS. The Intel 5000P chipset contains two main components: Memory Controller Hub (MCH) for the host bridge and the I/O controller hub for the I/O subsystem. The Intel 5000P chipset uses the ® ...

  • Page 16

    ... Error Correcting Code Enterprise South Bridge 2. Fully Buffered DDR2 One electrical interface to one or more Fully Buffered DDR2 DIMM. Processor Front-Side Bus. This is the bus that connects the processor to the MCH. Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Introduction ...

  • Page 17

    ... Input/Output. 2. When used as a qualifier to a transaction type, specifies that transaction targets Intel architecture-specific I/O space. (e.g., I/O read) 6th Generation I/O controller Hub. The I/O Controller Hub component that contains the legacy I/O functions. It communicates with the MCH over a proprietary interconnect called the DMI interface ...

  • Page 18

    ... Commonly refers to memory writes. The physical PCI bus that is driven directly by the Intel 631xESB/632xESB I/O Controller Hub component. Communication between PCI and the MCH occurs over ESI. Note that even though the Primary PCI bus is referred to as PCI it is not PCI Bus 0 from a configuration standpoint ...

  • Page 19

    ... SDDC SDR SDRAM SEC/DED Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Description Redundant Array of Independent Disks. RAID improves performance by disk striping, which interleaves bytes or groups of bytes across multiple drives, so more than one disk is reading and writing simultaneously. Fault tolerance is achieved by mirroring or parity. ...

  • Page 20

    ... A means of ensuring cache coherency by monitoring all coherent accesses on a common multi-drop bus to determine if an access is to information resident within a cache. The Intel® 5000P MCH ensures coherency by initiating snoops on the processor busses with the address of any line that might appear in a cache on that bus. ...

  • Page 21

    ... Intel Xeon 5100 series. The MCH supports 36 bit addressability for a total physical memory. The Dual-Core Intel Xeon 5000 Series has cache, a 266 MHz (1066 MTS) system bus and Dual-Core Intel Xeon 5100 Series has shared L2 cache, a 333 MHz (1333 MTS) system bus. They are fabricated using a 65nm process in a 771-pin LGA package ...

  • Page 22

    ... BIOS interface controller. Additionally the Intel 631xESB/632xESB I/O Controller Hub contains a PCI interface controller, Azalia / AC’97 digital controller, integrated LAN controller, an ASF controller and a ESI for communication with the MCH. The Intel 631xESB/632xESB I/O Controller Hub component provides the data buffering and interface arbitration required to ensure that system interfaces operate efficiently and provide the bandwidth necessary to enable the system to obtain peak performance ...

  • Page 23

    ... Intel® 631xESB/632xESB Azalia or AC’97 3 codec support 6 SATA Ports 1 PATA Port Intel® 82563EB Network Connection (Dual Port) PHY RJ45 Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet P1 P2 1066/1333 MTS System Bus PCI-E x4 ESI 2 GB/s 2 GB/s I/O Controller Hub ...

  • Page 24

    ... Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Introduction ...

  • Page 25

    ... Signal Description This section provides a detailed description of MCH signals. The signals are arranged in functional groups according to their associated interface. The signals presented in this section may not be present in all Intel 5000 Series Chipsets. To determine if a signal particular version, consult conventions are used: The terms assertion and deassertion are to avoid confusion when working with a mix of active-high and active-low signals ...

  • Page 26

    ... Denotes an active low signal or bus. Table 2-2 lists the reference terminology used for signal types. Table 2-2. Buffer Signal Types Buffer Direction I Input signal O Output signal A Analog I/O Bidirectional (input/output) signal 26 Expands to Description Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Signal Description ...

  • Page 27

    ... FSB0BREQ[1:0]# FSB0D[63:0]# FSB0DBI[3:0]# FSB0DBSY# FSB0DEFER# Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Type I/O Processor 0 Address Bus: FSB0A[35:3]# connect to the processor address bus. During processor cycles, FSB0A[35:3]# are inputs. The MCH drives FSB0A[35:3]# during snoop cycles on behalf of ESI and AGP/Secondary PCI initiators ...

  • Page 28

    ... O Processor 0 Reset: The FSB0RESET# pin is an output from the MCH. The MCH asserts FSB0RESET# while RSTIN# (PCIRST# from Intel 631xESB/ 632xESB I/O Controller Hub) is asserted and for approximately 1 ms after RSTIN# is deasserted. The FSB0RESET# allows the processors to begin execution in a known state ...

  • Page 29

    ... FSB1BREQ[1:0]# FSB1D[63:0]# FSB1DBI[3:0]# FSB1DBSY# FSB1DEFER# Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Type I/O Processor 1 Address Bus: FSB1A[35:3]# connect to the processor address bus. During processor cycles, FSB1A[35:3]# are inputs. The MCH drives FSB1A[35:3]# during snoop cycles on behalf of ESI and AGP/Secondary PCI initiators ...

  • Page 30

    ... O Processor 1 Reset: The FSB1RESET# pin is an output from the MCH. The MCH asserts FSB1RESET# while RSTIN# (PCIRST# from Intel 631xESB/ 632xESB I/O Controller Hub) is asserted and for approximately 1 ms after RSTIN# is deasserted. The FSB1RESET# allows the processors to begin execution in a known state ...

  • Page 31

    ... FB-DIMM Channel 1 Signal Name FBD1NBIN[13:0] FBD1NBIP[13:0] FBD1SBON[9:0] FBD1SBOP[9:0] Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Type FB-DIMM Bypass Bias Input for Band Gap Circuit: FB-DIMM Transmitter Swing Bias: FB-DIMM On-die Impedance Compensation: Type FB-DIMM Clock Negative: Core Clock Negative Phase ...

  • Page 32

    ... PCI Express Band Gap VCC: Band Gap Voltage PCI Express VSS: Analog Voltage for PCI Express PLL: PCI Express Band Gap VSS: Band Gap Voltage PCI Express Port Width Strapping Pins: Other Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Signal Description Description Description Description ...

  • Page 33

    ... Signal Description 2.3.2 PCI Express Port 0, Enterprise South Bridge Interface (ESI) PCI Express port port dedicated to providing the ESI link between the Intel 5000P chipset MCH and the Intel 631xESB/632xESB I/O Controller Hub. Signal Name PE0RP[3:0] PE0RN[3:0] PE0TP[3:0] PE0TN[3:0] 2.3.3 PCI Express Port 2 PCI Express port port ...

  • Page 34

    ... PCI Express Port 7 Positive Phase Inbound: (Receive) Signals I PCI Express Port 7 Negative Phase Inbound: (Receive) Signals O PCI Express Port 7 Positive Phase Outbound: (Transmit) Signals O PCI Express Port 7 Negative Phase Outbound: (Transmit) Signals Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Signal Description Description Description Description Description ...

  • Page 35

    ... JTAG Bus Signal List Signal Name TCK TDI TDO TMS TRST# Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Type I/O Slave SMB Clock: System Management Bus Clock I/O Slave SMB Data: SMB Address/Data I/O PCI SMB Clock: PCI Hot-Plug Master VPI, System Management Bus Clock ...

  • Page 36

    ... Core VSS: Analog Voltage for PLL O Error Output: Error output signal: ERR[0] = Correctable and recoverable error from the memory subsystem ERR[1] = Uncorrectable error from the Intel® 5000P MCH ERR[2] = Fatal error from the Intel® 5000P MCH Processor Bus Compensation: Processor Bus Compensation: ...

  • Page 37

    ... Signal Description • Clock Valid Timing: • BUSCLK must be valid at least 2ms prior to rising edge of PWRGOOD. Figure 2-1. Intel 5000P Chipset Clock and Reset Requirements Power Rails PWRGOOD RESET# BUSCLK Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet ~100ms 2ms 1ms 37 ...

  • Page 38

    ... Straps Straps Fuses Array Init T17 sampled inactive downloaded Reset T12 initialization Figure 2-4. Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Signal Description T14 T15 DMI handshake done Done Init Level full operation T14 T15 DMI handshake done Done ...

  • Page 39

    ... PLL's Sticky Bit Enable SYRE.SAVCFG 2.10.1.4 RESETI# Retriggering Limitations Figure 2-5 shows the timing for a RESETI# retrigger. Figure 2-5. RESETI# Retriggering Limitations RESETI# Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet T6 T11 T10 T13 T4 Array Init T17 Done Reset Init ...

  • Page 40

    ... T17 CPU_RESET_DONE capture timer Notes the Intel 5000P chipset B0 RTL, the T11 duration is implemented through a counter with max value of 162,000 core clocks. For 333 Mhz, this gives a period of 486 us for the POC setup time while @266 Mhz, the period is 607.5 us. 40 ...

  • Page 41

    ... No guarantee can be issued as to the final state of the EEPROM in this situation. The Intel® 5000P MCH cannot meet the SPD data t specification. Since the Intel® 5000P MCH floats the data output into a pull-up on the platform, a read will not degrade to a write. However, if the PWRGOOD deassertion occurs after the EEPROM has received the write bit, the data will be corrupted ...

  • Page 42

    ... Controller Hub Power Good Logic Processor Processor R ESET # R ESET #'s RE SETI# Intel® 5000P chipset PLTR ST# Intel Processor Processor INIT# Intel® 631xESB/ 632xESB I/O Controller Hub Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Signal Description chipset R ESET # INIT# ...

  • Page 43

    ... Signal Description 2.11.1 Intel 5000P Customer Reference Platform (SRP) Reset Topology Typical platform level reset implementation is described in the Dual-Core Intel Processor 5000 series (1066 MHz) and Intel Guide (PDG). 2.12 Signals Used as Straps 2.12.1 Functional Straps The PEWIDTH signals are used to determine the widths of the 7 PCI Express ports. ...

  • Page 44

    ... Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Signal Description ...

  • Page 45

    ... Specification, Revision 2.3. All the registers are organized by bus, device, function, and so forth, as defined in the PCI-Express Base Specification, Revision 1.0a. The MCH supports registers in PCI Express extended space. All MCH registers in Intel 5000P Chipset appear on PCI Bus #0. In addition, the MCH registers can be accessed by a memory mapped register access mechanism (as MMIO), a PCI configuration access mechanism (only PCI space registers), and register access mechanisms through JTAG and SMBus ...

  • Page 46

    ... MCH and the Intel 631xESB/632xESB I/O Controller Hub are physically connected by the ESI interface; thus, from a configuration standpoint, the ESI interface is logically PCI bus result, all devices internal to the MCH and Intel 631xESB/632xESB I/O Controller Hub appear PCI bus 0. The system’s primary PCI expansion bus is ...

  • Page 47

    ... Device 19: Device 19, Function 0 is routed to the Debug and Miscellaneous registers. These devices reside at DID 25F3h. • Device 21: Device 21, Function 0, FBD Branch 0 Memory Map, Error Flag/Mask, and Channel Control registers. These devices reside at DID 25F5h. Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet 47 ...

  • Page 48

    ... Port 7 3.3 Routing Configuration Accesses The Intel 5000P Chipset MCH supports both PCI Type 0 and Type 1 configuration access mechanisms as defined in the PCI Local Bus Specification, Revision 2.3. PCI Revision 2.3 defines hierarchical PCI busses. Type 0 configuration access are used for registers located within a PCI device that resides on the local PCI bus ...

  • Page 49

    ... Bits 31:2 of the CONFIG_ADDRESS register will be translated to the A[31:2] field of the ESI request packet of the configuration cycle as shown in Figure 3-2. This configuration cycle will be sent over the ESI to Intel 631xESB/632xESB I/O Controller Hub. Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet ...

  • Page 50

    ... If the cycle is forwarded to the Intel 631xESB/632xESB I/O Controller Hub via ESI, the Intel 631xESB/632xESB I/O Controller Hub compares the non-zero Bus Number with the Secondary Bus Number and Subordinate Bus Number Registers of its PCI-to-PCI bridges to determine if the configuration cycle is meant for primary PCI bus, one of the Intel 631xESB/632xESB I/O Controller Hub’ ...

  • Page 51

    ... Special Device and Function Routing All devices in the Intel 5000P Chipset, Intel 5000Z Chipset and Intel 5000V Chipset MCH reside on Bus 0. The following table describes the devices and functions that the MCH implements or routes specially. The DIMM component designator consists of a three-digit code: the first digit is the branch, the second digit is the channel on the branch, and the third digit is the DIMM (FB-DIMM command “ ...

  • Page 52

    ... Have no effect but to Have no effect but to SSection 3.8, “Register Software must read- modify-write to preserve the value Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description Functio Device Comment Depending on what is connected to these 3 0 ports, some may not be accessible ...

  • Page 53

    ... Register Description 3.5 I/O Mapped Registers There are only two I/O addresses that affect Intel 5000P Chipset MCH state. The first address is the DWORD location (CF8h) references a read/write register that is named CONFIG_ADDRESS. The second DWORD address (CFCh) references a read/write register named CONFIG_DATA. These two addresses are used for the PCI CFCh / CF8h configuration access mechanism ...

  • Page 54

    ... BOFL1 FE60_C400 BOFL2 FE60_C800 BOFL3 FE60_CC00 SPAD0 FE60_D000 SPAD1 FE60_D400 SPAD2 FE60_D800 SPAD3 FE60_DC00 SPADS0 FE60_E000 SPADS1 FE60_E400 SPADS2 FE60_E800 SPADS3 FE60_EC00 AMBASE[31:0] FE61_4800 AMBASE[63:32] FE61_4C00 HECBASE FE61_6400 54 Memory Address Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description ...

  • Page 55

    ... PEXCTRL3 CTRL PMCAP PMCSR MSICTRL MSINXPTR MSIAR MSIDR PEXCAP PEXCAPL PEXDEVCAP PEXDEVSTS PEXDEVCTRL PEXLNKCAP PEXLNKSTS PEXLNKCTRL Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet VID 00h 04h PEXSLOTSTS RID 08h CLS 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch ...

  • Page 56

    ... PEX_SSER 170h R 174h 178h 17Ch Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description 180h 184h 188h 18Ch 190h 194h 198h 19Ch 1A0h 1A4h 1A8h 1ACh 1B0h 1B4h 1B8h ...

  • Page 57

    ... Register Description Table 3-10. Device 0, Function 0: PCI Express Interconnect-Built-In-Self-Test Registers Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet 300h PEX0IBCTL 304h PEX0IBSYMBUF 308h PEX0IBEXTCTL 30Ch PEX0IBLOOPCNT PEX0IBLN PEX0IBLN PEX0IBLN 310h S3 S2 DIO0IBER 314h 318h 31Ch 320h 324h 328h 32Ch 330h ...

  • Page 58

    ... PEXCTRL2 4Ch 50h 54h MSICAPID 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description PEXSLOTCAP 80h PEXSLOTCTRL 84h PEXRTCTRL 88h PEXRTSTS 8Ch 90h 94h 98h 9Ch A0h A4h ...

  • Page 59

    ... RPERRCMD RPERRSTS RPERRSID Intel 5000P Sequence chipset MCHSPCAPID PEX_ERR_DOCMD EMASK_UNCOR_PEX EMASK_COR_PEX EMASK_RP_PEX PEX_FAT_FERR PEX_NF_COR_FERR PEX_FAT_NERR PEX_NF_COR_NERR PEX_UNIT_FERR PEX_UNIT_NERR Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 128h 12Ch 130h 134h ...

  • Page 60

    ... Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description 380h 384h 388h PEX[3:2]IBDLYSYM 38Ch PEX[3:2]I 390h BLNS1 BLNS0 394h 398h 39Ch 3A0h 3A4h ...

  • Page 61

    ... PEXCTRL3 CTRL PMCAP PMCSR MSICTRL MSINXPTR MSIAR MSIDR PEXCAP PEXCAPL PEXDEVCAP PEXDEVSTS PEXDEVCTRL PEXLNKCAP PEXLNKSTS PEXLNKCTRL Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet VID 00h 04h PEXSLOTSTS RID 08h CLS 0Ch 10h 14h PBUSN 18h IOBASE 1Ch 20h 24h ...

  • Page 62

    ... PEX_SSER 170h R 174h 178h 17Ch Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description 180h 184h 188h 18Ch 190h 194h 198h 19Ch 1A0h 1A4h 1A8h 1ACh 1B0h 1B4h 1B8h ...

  • Page 63

    ... Register Description Table 3-16. Device 4, Function 0: PCI Express IBIST Registers Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet 300h PEX4IBCTL 304h PEX4IBSYMBUF 308h PEX4IBEXTCTL 30Ch PEX4IBLOOPCNT PEX4IBLN PEX4IBLN PEX4IBLN 310h S3 S2 314h 318h 31Ch 320h 324h 328h 32Ch 330h 334h ...

  • Page 64

    ... PEXCTRL2 4Ch 50h 54h MSICAPID 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description PEXSLOTCAP 80h PEXSLOTCTRL 84h PEXRTCTRL 88h PEXRTSTS 8Ch 90h 94h 98h 9Ch A0h A4h ...

  • Page 65

    ... HDRLOG3 RPERRCMD RPERRSTS RPERRSID Intel 5000P Chipset MCHSPCAPID PEX_ERR_DOCMD EMASK_UNCOR_PEX EMASK_COR_PEX EMASK_RP_PEX PEX_FAT_FERR PEX_NF_COR_FERR PEX_FAT_NERR PEX_NF_COR_NERR PEX_UNIT_FERR PEX_UNIT_NERR Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 128h 12Ch 130h 134h ...

  • Page 66

    ... Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description 380h 384h 388h PE[7:5]IBDLYSYM 38Ch PEX[7:5]I 390h BLNS1 BLNS0 394h 398h 39Ch 3A0h 3A4h ...

  • Page 67

    ... MAXAMB MAXCH AMBSELECT PERCH PAM2 PAM1 PAM0 PAM6 PAM5 PAM4 EXSMRTOP EXSMRC SMRAMC HECBASE REDIRBUCKETS REDIRCTL Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet VID 00h 04h RID 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h ...

  • Page 68

    ... GBLACT 60h RECMEMA THRTLOW 64h 68h 6Ch 70h 74h 78h 7Ch Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description MIR0 80h MIR1 84h MIR2 88h AMIR0 8Ch AMIR1 90h AMIR2 94h FERR_FAT_FBD 98h ...

  • Page 69

    ... Register Description Table 3-23. Device 16, Function 2: RAS DID CCR HDR SID SVID FERR_Global NERR_Global Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet VID 00h 04h RID 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch ...

  • Page 70

    ... FBDLVL0 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description MTR0 80h MTR1 84h MTR2 88h MTR3 8Ch DMIR0 90h DMIR1 94h DMIR2 98h ...

  • Page 71

    ... Register Description Table 3-25. Device 21, Function 0: FB-DIMM 0 IBIST Registers Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet 100h FBD0IBPORTCTL 104h FBD0IBTXPGCTL 108h FBD0IBPATBUF1 10Ch FBD0IBTXMSK 110h FBD0IBRXMSK 114h FBD0IBTXSHFT 118h FBD0IBRXSHFT 11Ch FBD0RXLNERR 120h FBD0IBRXPGCTL 124h FBD0IBPATBUF2 128h FBD0IBTXPAT2EN 12Ch ...

  • Page 72

    ... Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description 280h 284h 288h 28Ch 290h 294h 298h 29Ch 2A0h 2A4h 2A8h 2ACh 2B0h 2B4h ...

  • Page 73

    ... Register Description Table 3-27. Device 22, Function 0: FB-DIMM 2 IBST Registers Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet 100h FBD2IBPORTCTL 104h FBD2IBPGCTL 108h FBD2IBPATBUF 10Ch FBD2IBTXMSK 110h FBD2IBRXMSK 114h FBD2IBTXSHFT 118h FBD2IBRXSHFT 11Ch FBD2RXLNERR 120h FBD2IBRXPGCTL 124h FBD2IBPATBUF2 128h FBD2IBTXPAT2EN 12Ch ...

  • Page 74

    ... Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description 280h 284h 288h 28Ch 290h 294h 298h 29Ch 2A0h 2A4h 2A8h 2ACh 2B0h 2B4h ...

  • Page 75

    ... Register Description Device Function: 0 Offset: 00h Version: Intel 5000P Chipset ,Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 00h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 00h Version: Intel 5000P Chipset Device: 16 Function Offset: 00h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset ...

  • Page 76

    ... Read Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Express compatible device and function. Previously, a new value for RID was assigned for Intel chipsets for every . There need to provide an alternative value for software compatibility when a particular driver or patch unique to that stepping or an earlier stepping is required, for instance, to prevent Windows software from flagging differences in RID during device enumeration ...

  • Page 77

    ... Register Description value reflects the actual product stepping. To select the CRID value, BIOS/configuration software writes a key value of 79h to Bus 0, Device 0, Function 0 (ESI port) of the Intel 5000P Chipset MCH’s RID register at offset 08h. This sets the SRID/CRID register select flip-flop and causes the CRID to be returned when the RID is read at offset 08h. ...

  • Page 78

    ... Stepping Revision ID (SRID) The SRID is a 4-bit hardwired value assigned by Intel, based on product’s stepping. The SRID is not a directly addressable PCI register. The SRID value is reflected through the RID register when appropriately addressed. The 4 bits of the SRID are reflected as the two least significant bits of the major and minor revision field respectively ...

  • Page 79

    ... See Figure 3-3. Figure 3-3. Intel 5000P Chipset MCH implementation of SRID and CRID Registers 3.8.1.4 CCR - Class Code Register This register contains the Class Code for the device. Writes to this register have no effect ...

  • Page 80

    ... Offset: 09h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 17 Function: 0 Offset: 09h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 21 Function: 0 Offset: 09h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 22 ...

  • Page 81

    ... Offset: 0Eh Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 17 Function: 0 Offset: 0Eh Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 21 Function: 0 Offset: 0Eh Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 22 ...

  • Page 82

    ... A write to any of the above registers on the MCH will write to all of them. 82 Description Vendor Identification Number. The default value specifies Intel. Each byte of this register will be writable once. Second and successive writes to a byte will have no effect. Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description ...

  • Page 83

    ... ESI Subtractive decode Notes: a. Any request not falling in the above ranges will be subtractively decoded and sent to Intel 631xESB/632xESB I/O Controller Hub via the ESI The MCH allows programmable memory attributes on 13 Legacy memory segments of various sizes in the 640 Kilobytes to 1 Megabytes address range. Seven Programmable Attribute Map (PAM) Registers are used to support these features. Intel® ...

  • Page 84

    ... WE - Write Enable. When the host write accesses to the corresponding memory segment are claimed by the MCH and directed to main memory. Conversely, when the host write accesses are directed to ESI (Intel 631xESB/632xESB I/O Controller Hub directed to the PCI bus. The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or disabled ...

  • Page 85

    ... PAM2 - Programmable Attribute Map Register 2 This register controls the read, write, and shadowing attributes of the BIOS areas which extend from 0C 8000h -0C FFFF h. Device: 16 Function: 0 Offset: 5Bh Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr Default 7:6 RV 5:4 RW 3:2 RV Intel® ...

  • Page 86

    ... Device: 16 Function: 0 Offset: 5Bh Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr Default 1:0 RW 3.8.2.4 PAM3 - Programmable Attribute Map Register 3 This register controls the read, write, and shadowing attributes of the BIOS areas which extend from 0D 0000h - 0D 7FFFh. ...

  • Page 87

    ... PAM4 - Programmable Attribute Map Registers 4 This register controls the read, write, and shadowing attributes of the BIOS areas which extend from 0D 8000h - 0D FFFFh. Device: 16 Function: 0 Offset: 5Dh Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr Default 7:6 RV 5:4 RW 3:2 RV ...

  • Page 88

    ... Device: 16 Function: 0 Offset: 5Eh Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr Default 1:0 RW 3.8.2.7 PAM6 - Programmable Attribute Map Register 6 This register controls the read, write, and shadowing attributes of the BIOS areas which extend from 0E 8000h -0E FFFFh. ...

  • Page 89

    ... The Open, Close, and Lock bits function only when EXSMRC.G_SMRAME bit is set Also, the OPEN bit must be reset before the LOCK bit is set. Device: 16 Function: 0 Offset: 61h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr Default RWL 5 RW ...

  • Page 90

    ... The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MByte. Device: 16 Function: 0 Offset: 62h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr Default 7 RWL ...

  • Page 91

    ... This register defines the base address of the enhanced PCI Express configuration memory. Device: 16 Function: 0 Offset: 64h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr Default 31:24 RV Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet 1h ESMMTOP: Top of Extended SMM Space (TSEG) This field contains the address that corresponds to address bits ...

  • Page 92

    ... AMBPRESENT for each AMB on the platform. There are up to eight functions per AMB component with 256 B of register space per function. Intel 5000V Chipset supports only 2 FB-DIMM channels. For more information on the Intel 5000V Chipset differences see The MCH supports memory mapped register regions for software to access individual AMB configuration registers ...

  • Page 93

    ... MAXCH - Maximum Channel Number Register Device: 16 Function: 0 Offset: 56h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset, Bit Attr Default 7:0 RO Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Default AMBASE: This marks the 128KB memory-mapped registers region used for accessing AMB registers ...

  • Page 94

    ... MCH supports for AMB configuration register access. This register applies only to DIMM modules in the FB-DIMM channel, that is, those AMB with DS[3:0] encoding from 0h to 7h. Device: 16 Function: 0 Offset: 57h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr Default 7:0 RO 3.8.3.6 Map to AMB Registers In Table 3-30, each 2 KB range is mapped to individual AMB registers by address translation of MCH ...

  • Page 95

    ... REDIRCTL - Redirection Control Register This register controls the priority algorithm of the XTPR interrupt redirection mechanism. Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet map to channel_1, AMB_9 registers map to channel_1, AMB_A registers map to channel_1, AMB_B registers map to channel_1, AMB_C registers ...

  • Page 96

    ... Device: 16 Function: 0 Offset: 6Eh Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 15: 11:8 RW 7:4 RW 3:0 RW 3.8.4.2 REDIRBUCKETS - Redirection Bucket Number Register This register allows software to read the current hardware bucket number assigned to each XTPR register. . Device: 16 Function: ...

  • Page 97

    ... Enables the Chipset to use the “BNR independent of BINIT” feature set. i.e no dependency is required between BNR and BINIT. Refer to the BNR#, BINIT# sampling rules in the Intel® Pentium® 4 and Intel® Xeon® Processor External Hardware Specification, Rev 2.5, Ref#14035 ...

  • Page 98

    ... DMI port. Hence the data is always sent back only after the expiry of the DCRT field at the heartbeat boundary sticky through reset to permit to allow different types of BIOS flows that may require a hard reset of the Intel 5000P Chipset MCH. Maximum value is 4095 core clocks A default of 2047 clocks (7FFh) is used. ...

  • Page 99

    ... They are also aliased to fixed memory addresses. Device: 16 Function: 0 Offset: ECh, E8h, E4h, E0h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 31:0 RWST 00000000h Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet 1 BUSPARK: Request Bus Parking Disable If set, A[15]# is asserted and the processor may not park on the system bus ...

  • Page 100

    ... SFBYPASS: Snoop Filter Bypass enabled disabled Note: The output of the fuse “SF CHOP” is gated appropriately with this register field viz. SFBYPASS for further internal decoding by Intel 5000P Chipset MCH. The fuse has overriding effect. 0h Reserved. Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet ...

  • Page 101

    ... Register Description Device: 16 Function: 0 Offset: 7Ch, 74h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr Default 31 3.8.6.3 XTPR[7:0] - External Task Priority Register These registers control redirectable interrupt priority for xAPIC agents connected to the MCH four agents on each bus are supported. These agents may be two dual core processors each with two threads or four single core processors ...

  • Page 102

    ... Master Abort (reads return all ones, writes dropped) any accesses to it. Note that configuration accesses to the unconnected port will still be allowed to permit device remapping, hot-plug and so forth. Table 3-32. When Will a Intel 5000P Chipset PCI Express Device be Accessible? (Sheet PCI ...

  • Page 103

    ... Register Description Table 3-32. When Will a Intel 5000P Chipset PCI Express Device be Accessible? (Sheet PCI Express Device Port Figure 3-4 illustrates how each PCI Express port’s configuration space appears to software. Each PCI Express port’s configuration space has four regions: • ...

  • Page 104

    ... PCI Express ports uniquely while the ESI port is referred by index 0. 104 0xFFF Intel® 5000P Chipset Advanced Error Reporting 0x140 PCI-Express Advanced Error Reporting 0x100 PCI-Express Capability MSI Capability PM Capability 0x40 CAP_PTR P2P 0x00 Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description ...

  • Page 105

    ... INTxDisable: Interrupt Disable Controls the ability of the PCI Express port to generate INTx messages. This bit does not affect the ability of the Intel 5000P Chipset MCH to route interrupt messages received at the PCI Express port. However, this bit controls the generation of legacy interrupts to the DMI for PCI Express ...

  • Page 106

    ... When the CPURESET# signal is asserted during a power good or hard reset and after the DMI completes its training, the LPC device in the Intel 631xESB/632xESB I/O Controller Hub (or other NIC/SIO4 cards could potentially send inbound requests even before the CPURESET# is deassserted. This corner case is handled by the BME filtration in the Intel 5000P Chipset MCH’ ...

  • Page 107

    ... PCI-PCI bridge embedded in the selected PCI Express cluster of the MCH. Device: 0, 2-3 Function: 0 Offset: 06h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 06h Version: Intel 5000Z Chipset ...

  • Page 108

    ... Device: 0, 2-3 Function: 0 Offset: 06h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 06h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 06h Version: Intel 5000P Chipset Bit Attr Default 2:0 RV 3.8.8.3 CLS[7: Cache Line Size This register contains the Cache Line Size and is set by BIOS/Operating system ...

  • Page 109

    ... EXP_ROM[0]: Expansion ROM Registers The ESI port (device 0, function 0) does not implement any Base address registers in the Intel 5000P Chipset MCH from offset 10h to 24h. Similarly no Expansion ROM base address register is defined in offset 30h. Also no Cardbus CIS pointer is defined in offset 28h. The MIN_GNT (offset 3Eh) and MAX_LAT (3Fh) registers are also not implemented as they are not applicable to the ESI interface. Intel® ...

  • Page 110

    ... PBUSN[7:2] - Primary Bus Number This register identifies the bus number on the on the primary side (MCH) of the PCI Express port. Device: 2-3 Function: 0 Offset: 18h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 18h Version: Intel 5000Z Chipset Device: ...

  • Page 111

    ... PCI Express interface. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to devices subordinate to the secondary PCI Express port. Device: 2-3 Function: 0 Offset: 1Ah Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 1Ah Version: Intel 5000Z Chipset Device: ...

  • Page 112

    ... KB boundary while the top of the region specified by IO_LIMIT will be one less than multiple. Refer to Chipset Platform Specification. Device: 2-3 Function: 0 Offset: 1Ch Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 1Ch Version: Intel 5000Z Chipset Device: ...

  • Page 113

    ... PCI Express side) of the “virtual” PCI-PCI bridge embedded within MCH. K Device: 2-3 Function: 0 Offset: 1Eh Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 1Eh Version: Intel 5000Z Chipset Device: ...

  • Page 114

    ... PCI Express port receives a Completion marked poisoned •The PCI Express port poisons a write Request If the Parity Error Response Enable bit is cleared, this bit is never set. Refer to Table 3-33 for details on the data parity error handling matrix in the Intel 5000P Chipset MCH. 0 SFB2BTC: Fast Back-to-Back Transactions Capable Not applicable to PCI Express ...

  • Page 115

    ... Memory Limit register) are FFFFFh. Thus, the bottom of the defined memory address range will be aligned boundary and the top of the defined memory address range will be one less than boundary. Refer to Section 4.4.3 in the Intel 5000P Chipset programmer’s guide for further details on address mapping. Device: 2-3 ...

  • Page 116

    ... There is no provision in the MCH hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed. Device: 2-3 Function: 0 Offset: 22h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 22h Version: Intel 5000Z Chipset Device: ...

  • Page 117

    ... A[31:20] of the 32 bit address. This register must be initialized by the configuration software. For the purpose of address decode address bits A[19:0] are assumed FFFFh. Device: 2-3 Function: 0 Offset: 26h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 26h Version: Intel 5000P Chipset Bit ...

  • Page 118

    ... Device: 2-3 Function: 0 Offset: 26h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 26h Version: Intel 5000P Chipset Bit Attr Default 3:0 RO 3.8.8.20 PMBU[7:2] - Prefetchable Memory Base (Upper 32 bits) The Prefetchable Base Upper 32 bits and Prefetchable Limit Upper 32 bits registers are extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers ...

  • Page 119

    ... Register Description 3.8.8.21 PMLU[7:2] - Prefetchable Memory Limit (Upper 32 bits) Device: 2-3 Function: 0 Offset: 2Ch Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 2Ch Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 2Ch Version: Intel 5000P Chipset ...

  • Page 120

    ... This register RO and is provided for backwards compatibility Device: 0, 2-3 Function: 0 Offset: 3Ch Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 3Ch Version: Intel 5000Z Chipset ...

  • Page 121

    ... SBUSRESET field to train the link. When this SBUSRESET bit is cleared after the MCH enters the “hot-reset” state, the Intel 5000P Chipset MCH will initiate operations to move to “detect” state and then train the link (polling, configuration, L0 (link-up)) after sending at least 2 TS1 and receiving 1 TS1 with the HotReset bit set in the training control field of TS1 and waiting for 2ms in the Hot-reset state ...

  • Page 122

    ... Device: 2-3 Function: 0 Offset: 3Eh Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 3Eh Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 3Eh Version: Intel 5000P Chipset Bit Attr Default 122 0 MAMODE: Master Abort Mode Not applicable to PCI Express ...

  • Page 123

    ... PEXLWSTPCTRL: PCI Express Link Width Strap Control Register This register provides the ability to change the PCI Express link width through software control. Normally, the Intel 5000P Chipset MCH will use the PEWIDTH[3:0] pins to train the links. However, if BIOS needs the ability to circumvent the pin strappings and ...

  • Page 124

    ... IOU cluster will ignore the external pin strap (PEWIDTH[3:0] and use the described table for configuring the link width. The values will take effect after a hard reset. Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description ...

  • Page 125

    ... RSVD 3'b001 invalid 3'b010 x4 RSVD 3'b011 invalid 3'b100 invalid 3'b101 invalid 3'b110 invalid 3'b111 x4 RSVD Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet GIO Port (IOU1) GPMNXT0 Port2 Port3 [2:0] Port4 (IOU1 3'b000 x4 3'b001 x8 x8 N/A 3'b010 x4 3'b011 x8 ...

  • Page 126

    ... Suggested value: 1 Note: When both TIMEOUT_ENABLE_CFG and TIMEOUT_ENABLE fields are set to 0, the Intel 5000P will assume an infinite completion time for the respective transactions. Hence the system is dependent on the end device returning the completion response at some point in time, else it will result in a hang. ...

  • Page 127

    ... B completion combining) due an MCH B2 silicon issue, especially when MPS is configured to 256 B. 0 COALESCE_FORCE: Force coalescing of accesses. When 1, forces Intel 5000P Chipset MCH to wait for all coalescable data before sending the transaction as opposed to forwarding as much as possible. 0: Normal operation 1: wait to coalesce data Note strongly recommended that COALESCE_FORCE should not be set to ‘ ...

  • Page 128

    ... Hotplug, presence, MRL and other events defined in 1 DIS_VPP: Disable VPP The Intel 5000P Chipset MCH will use this bit to decide whether the VPP is valid or not for the given PCI Express port as set by configuration software. For example, to distinguish HP events for a legacy card or PCI Express port module, this bit can be used ...

  • Page 129

    ... PEXCTRL2[7:2,0]: PCI Express Control Register 2 This is an auxiliary control register for PCI Express port specific debug/defeature operations. Device: 0, 2-3 Function: 0 Offset: 4Ch Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 4Ch Version: Intel 5000Z Chipset Device: ...

  • Page 130

    ... PME_TURN_OFF: Send PME Turn Off Message When set, the Intel 5000 Chipset MCH will issue a PME Turn Off Message to all enabled PCI Express ports excluding the ESI port. The Intel 5000 Chipset MCH will clear this bit once the Message is sent. ...

  • Page 131

    ... PCI Express Power Management Capability Structure The Intel 5000P Chipset MCH PCI Express port provides basic power management capabilities to handle PM events for compatibility. The PCI Express ports can be placed in a pseudo D3 hot state but it does have real power savings and works were in the D0 mode ...

  • Page 132

    ... MCH. 132 PMES: PME Support Identifies power states in the Intel 5000P Chipset MCH which can send an “Assert_PMEGPE/Deassert PMEGPE” message. Bits 31, 30 and 27 must be set to '1' for PCI-PCI bridge structures representing ports on root complexes. The definition of these bits is taken from the PCI Bus Power Management Interface Specification Revision 1 ...

  • Page 133

    ... This PME Status is a sticky bit. When set, the PCI Express port generates a PME internally independent of the PMEEN bit defined below. Software clears this bit by writing a ‘1’ when it has been completed root port, the Intel 5000P Chipset MCH will never set this bit, because it never generates a PME internally independent of the PMEEN bit. 0h ...

  • Page 134

    ... MSI mechanism is supported by the following registers: the MSICAPID, MSINXPTR, MSICTRL, MSIAR and MSIDR register described below. 3.8.10.1 MSICAPID[7: MSI Capability ID Device: 0, 2-3 Function: 0 Offset: 58h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 58h Version: Intel 5000Z Chipset Device: 4-7 ...

  • Page 135

    ... The software sets this bit to select legacy interrupts or transmit MSI messages. 0: Disables MSI from being generated. 1: Enables the Intel 5000P Chipset MCH to use MSI messages to request context specific service through register bits defined in the for events such as hot-plug, PM, RAS. Refer to the Intel 5000P Chipset Programming Guide for details on the legacy, ACPI and interrupt generation events ...

  • Page 136

    ... The MSI Address Register (MSIAR) contains the system specific address information to route MSI interrupts and is broken into its constituent fields. Device: 0, 2-3 Function: 0 Offset: 5Ch Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 5Ch Version: Intel 5000Z Chipset ...

  • Page 137

    ... Register Description Device: 0, 2-3 Function: 0 Offset: 60h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 60h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 60h Version: Intel 5000P Chipset Bit Attr Default 13:11 RW 10:8 RW 7:0 RW Table 3-34 ...

  • Page 138

    ... The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 2.3 configuration space. Device: 0, 2-3 Function: 0 Offset: 6Ch Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 6Ch Version: Intel 5000Z Chipset ...

  • Page 139

    ... DPT: Device/Port Type This field identifies the type of device set to 0100 as defined in the spec since the PCI Express port is a “root port” in the Intel 5000P Chipset MCH. VERS: Capability Version This field identifies the version of the PCI Express capability structure. Set to 0001 by PCI SIG ...

  • Page 140

    ... Intel 5000P Chipset MCH Root complex. . Hardwired to 0h 00h CSPLV: Captured Slot Power Limit Value This field specifies upper limit on power supplied by a slot in an upstream port. It does not apply to Intel 5000P Chipset MCH Root complex. . Hardwired to 00h 0h Reserved 0 PIPD: Power Indicator Present on Device This bit when set indicates that a Power Indicator is implemented ...

  • Page 141

    ... This field indicates the maximum payload size that the PCI Express port can support for TLPs. 001: 256 B max payload size Others - Reserved Note that the Intel 5000P Chipset MCH only supports maximum of 256 B payload (for example, writes, read completions) for each TLP and violations will be flagged as PCI Express errors Description ...

  • Page 142

    ... The PCI Express Device Control register controls PCI Express specific capabilities parameters associated with this port. Device: 0, 2-3 Function: 0 Offset: 74h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 74h Version: Intel 5000Z Chipset Device: ...

  • Page 143

    ... MPS: Max Payload Size This field is set by configuration software for the maximum TLP payload size for the PCI Express port receiver, the Intel 5000P Chipset MCH must handle TLPs as large as the set value transmitter, it must not generate TLPs exceeding the set value. Permissible values that can be programmed ...

  • Page 144

    ... Device: 0, 2-3 Function: 0 Offset: 74h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 74h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 74h Version: Intel 5000P Chipset Bit Attr Default 3.8.11.5 PEXDEVSTS[7: PCI Express Device Status Register The PCI Express Device Status register provides information about PCI Express device specific parameters associated with this port ...

  • Page 145

    ... Register Description Device: 0, 2-3 Function: 0 Offset: 76h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 76h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 76h Version: Intel 5000P Chipset Bit Attr Default 3 RWC 2 RWC 1 RWC ...

  • Page 146

    ... More than 64us The Intel 5000P Chipset MCH does not support L1 acceptable latency and is set to the maximum value for safety 7h L0sEL: L0s Exit Latency This field indicates the L0s exit latency (i.e L0s to L0) for the PCI Express port ...

  • Page 147

    ... Disabled 01: L0s Entry Supported 10: Reserved 11: L0s and L1 Supported The Intel 5000P Chipset MCH does not initiate L0s active state Power Management but it does permit a downstream device from placing the link in L0s MLW: Maximum Link Width This field indicates the maximum width of the given PCI Express Link attached to the port ...

  • Page 148

    ... This field controls the level of active state power management supported on the given PCI Express port. 00: Disabled 01: L0s Entry Supported 10: Reserved 11: L0s and L1 Supported Note: This has no effect on the Intel 5000P Chipset MCH. Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description Description ...

  • Page 149

    ... RO Notes: a. The NLNKWD field is set to a default value corresponding to x4 internally within the Intel 5000P Chipset MCH. Note that this field is a don’t care until training is completed for the link. Software should not use this field to determine whether a link is up (enabled) or not. ...

  • Page 150

    ... This field indicates that a device in this slot may be removed from the system without prior notification. 0: Indicates that hot-plug surprise is not supported 1: Indicates that hot-plug surprise is supported The Intel 5000P Chipset MCH does not support hot-plug surprise feature. Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description Value ...

  • Page 151

    ... Register Description Device: 0, 2-3 Function: 0 Offset: 80h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 80h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 80h Version: Intel 5000P Chipset Bit Attr Default 4 RWO 3 RWO 2 RWO ...

  • Page 152

    ... This bit indicates the current state of the Power Indicator of the PCI Express port 00: Reserved. 01: On 10: Blink (The Intel 5000P Chipset MCH drives 1.5 Hz square wave for Chassis mounted LEDs in the case of legacy card form factor for PCI Express devices) 11: Off Default is set to 11b (OFF) When this field is written, the Intel 5000P Chipset MCH sends appropriate POWER_INDICATOR messages through the PCI Express port ...

  • Page 153

    ... Blink (The Intel 5000P Chipset MCH drives 1.5 Hz square wave) 11: Off Default is set to 11b (OFF) When this field is written, the Intel 5000P Chipset MCH sends appropriate ATTENTION_INDICATOR messages through the PCI Express port. For legacy card based PCI Express devices, the event is signaled via the virtual pins of the Intel 5000P Chipset MCH, in addition ...

  • Page 154

    ... Device: 0, 2-3 Function: 0 Offset: 84h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 84h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 84h Version: Intel 5000P Chipset Bit Attr Default 0 RW 3.8.11.11 PEXSLOTSTS[7: PCI Express Slot Status Register The PCI Express Slot Status register defines important status information for operations such as hot-plug and Power Management ...

  • Page 155

    ... Register Description Device: 0, 2-3 Function: 0 Offset: 86h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 86h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 86h Version: Intel 5000P Chipset Bit Attr Default 3 RWC 2 RWC 1 RWC ...

  • Page 156

    ... HPINTEN MSIEN Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet Register Description Intel® 5000P Chipset Sends desassert_HPGP E message via DMI when the when the respective bits PEXSLOTSTS str cleared (wired-OR) OR) Intel® 5000P Chipset Sends desassert_INTx message via DMI ...

  • Page 157

    ... PEXRTCTRL[7: PCI Express Root Control Register The PCI Express Root Control register specifies parameters specific to the root complex port. Device: 0, 2-3 Function: 0 Offset: 88h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 88h Version: Intel 5000Z Chipset Device: ...

  • Page 158

    ... PMESTATUS bit in each of the PEXRTSTS[2:7] registers are wired OR together and when set, the MCH will send the “Assert_PMEGPE” message to the Intel 631xESB/632xESB I/O Controller Hub for power management. When all the bits are clear, it will send the “Deassert_PMEGPE” message. PMEINTEN defined in PEXRTCTRL has to be set for PM interrupts to be generated ...

  • Page 159

    ... SAC: STOPGRANT ACK COUNT This field tracks the number of Stop Grant acks received from the FSBs. The MCH will forward the last StopGrantAck received from the FSB to the Intel 631xESB/632xESB I/O Controller Hub using the “Req_C2” command. Software is expected to set this field to “THREADs-1” where the variable “THREAD” is the total number of logical threads present in the system (currently can handle up to 16) ...

  • Page 160

    ... Device: 0, 2-3 Function: 0 Offset: 100h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 100h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 100h Version: Intel 5000P Chipset Bit Attr Default 31:20 RO 140h 19:16 RO 15:0 RO 0001h 3 ...

  • Page 161

    ... UNCERRSEV register) determines which bit in the PEX_FAT_FERR, PEX_NF_COR_FERR, PEX_FAT_NERR, PEX_NF_COR_NERR registers get recorded. These error log registers are described starting from Section 3.8.12.24. Device: 0 Function: 0 Offset: 104h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 31: RWCST 20 RWCST ...

  • Page 162

    ... Device: 0 Function: 0 Offset: 104h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 11 RWST 4 RWCST 3 RWCST 3.8.12.4 UNCERRMSK[7:2] - Uncorrectable Error Mask This register masks uncorrectable errors from the UNCERRSTS[2:7] register from being signaled. Device: 2-3 Function: 0 Offset: 108h ...

  • Page 163

    ... UNCERRMSK[0] - Uncorrectable Error Mask For ESI Port This register masks uncorrectable errors from the UNCERRSTS[0] register (ESI port) from being signaled. Device: 0 Function: 0 Offset: 108h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 31: RWST 20 RWST 19 RV ...

  • Page 164

    ... Device: 0 Function: 0 Offset: 10Ch Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 17 RWST 16 RWST 15 RWST 14 RWST 13 RWST 12 RWST 11 RWST 4 RWST 3 RWST UNCERRSEV[7:2] 3.8.12.7 This register indicates the severity of the uncorrectable errors. An error is reported as fatal when the corresponding error bit in the severity register is set. If the bit is cleared, the corresponding error is considered non-fatal ...

  • Page 165

    ... Register Description Device: 2-3 Function: 0 Offset: 10Ch Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 10Ch Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 10Ch Version: Intel 5000P Chipset Bit Attr 14 RWST 13 RWST 12 RWST 11:6 ...

  • Page 166

    ... Device: 0, 2-3 Function: 0 Offset: 110h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 110h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 110h Version: Intel 5000P Chipset Bit Attr 7 RWCST 6 RWCST 5 RWCST 3.8.12.9 CORERRMSK[7: Correctable Error Mask This register masks correctable errors from being signalled ...

  • Page 167

    ... This register contains the first 32 bits of the header log locked down when the first uncorrectable error occurs. Headers of the subsequent errors are not logged. Device: 0, 2-3 Function: 0 Offset: 11Ch Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 11Ch Version: Intel 5000Z Chipset ...

  • Page 168

    ... Device: 0, 2-3 Function: 0 Offset: 120h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 120h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 120h Version: Intel 5000P Chipset Bit Attr Default 31:0 ROST 3.8.12.13 HDRLOG2[7: Header Log 2 This register contains the third 32 bits of the header log ...

  • Page 169

    ... Register Description 3.8.12.15 RPERRCMD[7: Root Port Error Command This register controls behavior upon detection of errors. Device: 0, 2-3 Function: 0 Offset: 12Ch Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 12Ch Version: Intel 5000Z Chipset Device: 4-7 ...

  • Page 170

    ... Device: 0, 2-3 Function: 0 Offset: 130h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 130h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 130h Version: Intel 5000P Chipset Bit Attr 31: RWCST 5 RWCST 4 RWCST 3 RWCST ...

  • Page 171

    ... Intel 5000P Chipset Bit Attr Default 31:16 ROST 15:0 ROST 3.8.12.18 Intel 5000P Chipset MCH SPCAPID[7: MCH Specific Capability ID This register identifies the capability structure and points to the next structure. Device: 0, 2-3 Function: 0 Offset: 140h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset ...

  • Page 172

    ... Device: 0, 2-3 Function: 0 Offset: 144h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 144h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 144h Version: Intel 5000P Chipset Bit Attr 31:8 RV 7:6 RW 5:4 RW 3:2 RW 1:0 RW 3.8.12.20 EMASK_UNCOR_PEX[0] - Uncorrectable Error Detect Mask For ESI This register masks (blocks) the detection of the selected error bits for the ESI port ...

  • Page 173

    ... Register Description Device: 0 Function: 0 Offset: 148h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr Default 31 3.8.12.21 EMASK_UNCOR_PEX[7:2] - Uncorrectable Error Detect Mask This register masks (blocks) the detection of the selected error bits. When a specific error is blocked, it does NOT get reported or logged. ...

  • Page 174

    ... Device: 2-3 Function: 0 Offset: 148h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 148h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 148h Version: Intel 5000P Chipset Bit Attr Default 11 3 3.8.12.22 EMASK_COR_PEX[7: Correctable Error Detect Mask This register masks (blocks) the detection of the selected bits ...

  • Page 175

    ... Register Description Device: 0, 2-3 Function: 0 Offset: 14Ch Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 14Ch Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 14Ch Version: Intel 5000P Chipset Bit Attr 0 RW 3.8.12.23 EMASK_RP_PEX[7: Root Port Error Detect Mask This register masks (blocks) the detection of the selected bits associated with the root port errors ...

  • Page 176

    ... Device: 0, 2-3 Function: 0 Offset: 154h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 154h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 154h Version: Intel 5000P Chipset Bit Attr 31: RWCST 11 RWCST 10 RWCST 9 RWCST 8 RWCST 7 RWCST ...

  • Page 177

    ... Register Description . Device: 0, 2-3 Function: 0 Offset: 158h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 158h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 158h Version: Intel 5000P Chipset Bit Attr 31: RWCST 16 RWCST 15 RWCST 14 RWCST ...

  • Page 178

    ... Device: 0, 2-3 Function: 0 Offset: 15Ch Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 15Ch Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 15Ch Version: Intel 5000P Chipset Bit Attr 31: RWCST 11 RWCST 10 RWCST 9 RWCST 8 RWCST 7 RWCST ...

  • Page 179

    ... Register Description Device: 0, 2-3 Function: 0 Offset: 160h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 160h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 160h Version: Intel 5000P Chipset Bit Attr 31: RWST 16 RWCST 15 RWCST 14 RWCST ...

  • Page 180

    ... Device: 2-3 Function: 0 Offset: 168h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Device: 4-5 Function: 0 Offset: 168h Version: Intel 5000Z Chipset Device: 4-7 Function: 0 Offset: 168h Version: Intel 5000P Chipset Bit Attr 31 RWCST 3.8.12.29 PEX_UNIT_NERR[7:2] - PCI Express Next Unit Error Register This register records the occurrence of subsequent unit errors that are specific to this PCI Express port caused by external activities ...

  • Page 181

    ... NERR_GLOBAL - Global Next Error Register Once an error has been logged in the FERR_GLOBAL, subsequent errors are logged in the NERR_GLOBAL register. . Device: 16 Function: 2 Offset: 44h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 31 RWCST 30 RWCST 29 RWCST 28 RWCST 27:25 ...

  • Page 182

    ... Device: 16 Function: 2 Offset: 44h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 21 RWCST 20 RWCST 19 RWCST 18 RWCST RWCST 15 RWCST 14 RWCST 13 RWCST 12 RWCST 11 RWCST 7 RWCST 6 RWCST 5 RWCST 4 RWCST 3 RWCST 2 RWCST RWCST 182 Default 0 Global_NERR_21: PCI Express Device 5 Fatal Error ...

  • Page 183

    ... NERR_FAT_FSB[1:0]: FSB Next Fatal Error Register This register logs all FSB subsequent errors after the FERR_FAT_FSB has logged the 1st fatal error. . Device: 16 Function: 0 Offset: 482h, 182h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 7 RWCST RWCST ...

  • Page 184

    ... RECFSB[1:0]: Recoverable FSB Error Log Register The following error log registers captures the FSB fields on the logging of an error in the corresponding FERR_NF_FSB Register. Device: 16 Function: 0 Offset: 488h, 188h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr Default 31:29 RV 28:24 ROST 23:21 ROST ...

  • Page 185

    ... Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 7:0 ROST 3.8.13.11 EMASK_FSB[1:0]: FSB Error Mask Register A ‘0’ in any field enables that error. Device: 16 Function: 0 Offset: 492h, 192h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 15 RWST 7 RWST 6 RWST 5 RWST 4 RV ...

  • Page 186

    ... This register enables the signaling of Err[2] when an error flag is set. Note that one and only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and MCERR_FSB for each of the corresponding bits. . Device: 16 Function: 0 Offset: 498h, 198h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 15 RWST 7 RWST 6 RWST ...

  • Page 187

    ... Register Description Device: 16 Function: 0 Offset: 494h, 194h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 15 RWST 7 RWST 6 RWST 5 RWST RWST 0 RWST 3.8.13.15 MCERR_FSB[1:0]: FSB MCERR Mask Register This register enables the signaling of MCERR when an error flag is set. Note that one and only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and MCERR_FSB for each of the corresponding bits ...

  • Page 188

    ... RWCST 1 RWCST 0 RWCST 3.8.13.19 NERR_NF_INT - Internal Next Non-Fatal Error Register Device: 16 Function: 2 Offset: C3h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 7 RWCST 188 Default 000 Reserved 0 B7Err: Multiple ECC error in any of the ways during SF lookup 0 Reserved ...

  • Page 189

    ... This register is not currently used as there are no correctable errors with in the internal data path of the MCH. Device: 16 Function: 2 Offset: C8h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 31:21 RV 20:13 ROST 12:11 RV Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet ...

  • Page 190

    ... This register enables the signaling of Err[2] when an error flag is set. Note that one and only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and MCERR_INT for each of the corresponding bits. Device: 16 Function: 2 Offset: D2h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 7 RWST 6 RWST 5 RWST 4 ...

  • Page 191

    ... This register enables the signaling of Err[0] when an error flag is set. Note that one and only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and MCERR_INT for each of the corresponding bits. Device: 16 Function: 2 Offset: D0h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 7 RWST 6 RWST 5 RWST 4 ...

  • Page 192

    ... INITDONE: Initialization Complete. This scratch bit communicates software state from Intel 5000P Chipset MCH to BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory array is complete. This bit has no effect on Intel 5000P Chipset MCH operation. Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet ...

  • Page 193

    ... FBDHPC.NEXTSTATE defines other characteristics of mirrored mode. The Intel 5000P Chipset MCH does not support mirroring while sparing is enabled: this bit should not be set if SPCPC.SPAREN is set. The Intel 5000P Chipset MCH does not support mirroring with demand scrub: this bit should not be set if DEMSEN is set. ...

  • Page 194

    ... Software should poll this bit after setting the Scrub Enable (SCRBEN) bit to determine when the operation has completed. If the Scrub enable bit is cleared midway during the scrub cycle, then the SCRBDONE bit will not be set and the Intel 5000P Chipset MCH will stop the scrub cycle immediately. ...

  • Page 195

    ... The Intel 5000P Chipset MCH will use an internal signal called GBLTHRT* from its combinatorial cluster for controlling open loop throttling MC.GTW_MODE=1, then the debug mode is enabled and the Intel 5000P Chipset MCH will use 2 windows for global activation logic to be valid. ...

  • Page 196

    ... A mid level throttling level that is applied when the temperature is in the middle range (above Tlow but below Tmid) and THRTCTRL.THRMHUNT is set or the THRTSTS.GBLTHRT* bit is set by the Global Throttling Window logic in the Intel 5000P Chipset MCH. The maximum value this field can be initialized by software is 168 (decimal). This corresponds to 672 activations per activation window and gives 100% BW ...

  • Page 197

    ... This field should be less than or equal to the THRTMID.THRTMIDLM. Description Reserved THRMODE: Thermal Throttle Mode 0: THRTSTS.THRMTHRT register is initialized by the Intel 5000P Chipset MCH such that they vary in range between THRTMID and THRTHI above Tmid (staircase) 1: THRTSTS.THRMTHRT register field is “slammed” to THRTHI above Tmid. THRMHUNT: Intelligent Thermal Throttle Enable 0: THRTSTS ...

  • Page 198

    ... The MC assumes that the Intel 5000P Chipset MCH is operating normally, that is not operating with only one FB-DIMM channel as in single channel mode this mode, the Intel 5000P Chipset MCH MC will operate such that only 1 channel (that is, branch 0, channel 0) is active and there can be one or more DIMMS present in Channel 0 ...

  • Page 199

    ... Register Description Device: 16 Function: 1 Offset: 160h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr 31:0 RWST 11111111h Table 3-38. FB-DIMM to Host Gear Ratio Mux FSB:Memory Frequency 333:333 267:267 400:400 333:267 267:333 267:333 Notes: a. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the respective memory gearing registers (no mix and match) ...

  • Page 200

    ... This register consists of eight nibbles of mux select data for the proper selection of gearing behavior on the Host to FB-DIMM path (south bound). Device: 16 Function: 1 Offset: 168h Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset Bit Attr Default 31:0 RWST 11111111h Table 3-40. Host to FB-DIMM Gear Ratio Mux Select FSB:Memory Frequency ...